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Intel FPGA I2C Agent Avalon-MM Host Bridge Core

Reza5
Beginner
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Hi,

 

I'm trying to use Intel FPGA I2C Agent Avalon-MM Host Bridge Core to read FPGA's memory content through I2C. But I'm stuck in the first step. I cannot make the IP work. 

 

I included .qsys and .qip files to my project and used the code in page 207 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf as my top module. But I couldn't compile the design.

 

Then I tried to change the top module code as the picture below. I could successfully compile the design and download it to MAX10 Development board. But the IP didn't work. It didn't generate the ACK bit at all. (I tested it experimentally)

Reza5_0-1696957198116.png

 

 

Is there any example or application note which explains how to utilize this IP? Do I need to make any changes in the Verilog/VHDL files generated by the IP Parameter Editor?

 

Here is my configuration for the IP. I tried to make it simple.

Reza5_1-1696957377575.png

 

 

I followed Random Address Read operation to read from the FPGA. The Master sends the FPGA address (0x55) with 0 for R/!W bit in the CONTROL BYTE. Then the master sends one address byte (0x50). Since it is on Byte Addressing mode = 1, the master then restarts and sends the CONTROL BYTE with 1 for R/!W bit. In this whole operation, the FPGA does not generate ACK bit.

Reza5_2-1696958191206.png

 

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RichardTanSY_Intel
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I can't find an example design for this IP.

 

However the example design below (1. based on SPI and 2. I2C master) could still be a good design reference starter.

 

1. MAX 10 - SPI Slave to Avalon Master Bridge for MAX10 Dev Kit

https://www.intel.com/content/www/us/en/design-example/715042/max-10-spi-slave-to-avalon-master-bridge-for-max10-dev-kit.html?wapkw=I2C%20Slave%20to%20Avalon-MM%20Master%20bridge%20Core

 

2. MAX 10 - I2C Remote System Update Example

https://www.intel.com/content/www/us/en/design-example/714746/max-10-i2c-remote-system-update-example.html?wapkw=I2C%20Intel%20FPGA%20ACK%20signal

 

Best Regards,

Richard Tan

 

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

 

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RichardTanSY_Intel
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We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support.

We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to let us know.

Thank you for reaching out to us!

 

Best Regards,

Richard Tan

 

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 


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Reza5
Beginner
559 Views

Hi Richard,

 

Sorry for late reply. I have read the second example design (I2C master), and I didn't help. I will take a look into the first one and let you know whether it worked or not.

 

Thanks,

Reza,

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