Intel® L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) IP for PCI Expres

[mark_lee]

Hi Team

      I  try to generate SR-IOV example  refer to the "Intel® L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) IP for PCI Express* User Guide "  to running on the  Stratix® 10 FPGA Development Kit  " DK-DEV-1SGX-L-A " .  When I select Device  " 1SG280HU2F50E2VG" , there have option to enable the sr-iov , 

  When I select Device  " 1SG280LU2F50E2VG" , there have not option to enable the sr-iov .

 Is the device 1SG280LU2F50E2VG does not support SR-IOV?

[KhaiChein_Y_Intel]

Hi,

I tried to create an example design using the settings that you have provided and keep others as default. The design example generation is successful.

May I know which software edition / version you are using? Can you use the latest version?

Thanks

Best regards,

KhaiY

[mark_lee]

Hi  KhaiChein

     I use the Quartus Prime Pro 21.1

     Does your example  select the device 1SG280LU2F50E2VG ?  and enable the SR-IOV?

[KhaiChein_Y_Intel]

Hi,

I am using 1SG280HU2F50E2VG. Please allow me some time to try using 1SG280LU2F50E2VG.

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi Mark,

Yes. Single Root I/O Virtualization (SR-IOV) support is added for H-Tile variants only.

You may refer to the release note https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/rn/rn-s10-pcie.pdf

Thanks

Best regards,

KhaiY

[mark_lee]

Hi  KhaiChein

       Thanks  a lot  for you answer.

[KhaiChein_Y_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best regards,

KhaiY