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Altera_Forum
Honored Contributor I
806 Views

Interconnect issue

Hi all experts. 

 

I have an issue regarding to interconnect. 

 

In detail, one of my interconnect is generated to be connected between master IP and slave IP. 

 

Slave IP is generating “read_req”, and it is sent to master IP through “interconnect” 

 

As you see below block diagram, the read request signal on “mpfe_0_slv_1_read” has to be transferred to “avalon_pipe_master_0_m0_read”. 

 

The high-lighted signals in modelsim captured image (Avalon_pipe_master_0_m0_read/mpfe_0_slv_1_read) are read request signal on Master/Slave port. 

 

However, the signal on the slave port doesn’t go on the master port. 

 

Does anyone know how to fix this problem?
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Altera_Forum
Honored Contributor I
30 Views

I presume you are using Qsys and these are two custom components. Is that correct? The Avalon spec doesn't have a "read request" signal, so in the Qsys component editor, what signal role have you given this signal? Do you mean that it's a "read" (i.e. read enable) signal? Check the Avalon spec here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pd...

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