Trying to interface HPS and FPGA for UART connection. Have done the interfacing using Qsys. The FPGA is Cyclone V DE1 SoC board. Compiling the code gives the following error. Error (35030): Partition "fpgahps_hps_0_hps_io_border:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity Error (35032): Output port "fpgahps:u0|fpgahps_hps_0:hps_0|fpgahps_hps_0_hps_io:hps_io|fpgahps_hps_0_hps_io_border:border|mem_dm[0]" on partition "fpgahps_hps_0_hps_io_border:border" must drive a top-level pin but is driving "" Error (35032): Output port "fpgahps:u0|fpgahps_hps_0:hps_0|fpgahps_hps_0_hps_io:hps_io|fpgahps_hps_0_hps_io_border:border|mem_dqs[0]" on partition "fpgahps_hps_0_hps_io_border:border" must drive a top-level pin but is driving "fpgahps:u0|fpgahps_hps_0:hps_0|fpgahps_hps_0_hps_io:hps_io|fpgahps_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|strobe_in"fpgahps is the name of the Qsys file.Can anybody help?
