Hello,
I am having trouble reading data from the DCFIFO and writing it into the RAM using the SGDMA.
At the moment, I have a rather simple setup:
av_st_data is connected to the output of the FIFO.
av_st_ready is connected to the read enable of the FIFO
valid, sop and eop are connected to not fifo empty.
That leads to the result that sop and eop are always equal, but that should not be the problem?
The SGDMA always turns to "busy" when started but does not seem to return any data nor enable at least av_st_ready, as the FIFO overflows even if the SGDMA is activated.
Thanks for your help
