Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21602 Discussions

Internal M9K in power saving mode

Altera_Forum
Honored Contributor II
‎08-15-2015 09:42 PM
1,064 Views

Hello, is there such a thing? I see clockena input, but it seems to just enable or disable latching of the data/address/we lines on the clock signal transition, and there's no such thing as "chip select" for the M9K block. 

Device: Cyclone III.
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎08-16-2015 07:22 AM
407 Views

No there isn't. Fpgas don't have any chip enables on base components

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.