Invalid JTAG configuration

[Altera_Forum]

I am using MAX10 10M50SAE-144C8GES installed on our board, with Quartus Prime 15.1, programming with USB Blaster rev C.  

I was debugging using SignalTap II, modifying the project, compiling and downloading it through the LogicTapII tool. At some point in the project development I got message "Invalid JTAG configuration" and was unable to program the MAX10 chip.  I tried to use programmer tool and it shows completion but the MAX10 chip is not actually programmed (the chip doesn't work). I changed both the board and the USB Blaster, got the same result. I tried USB Blaster with Altera 10M08 eval board and simple test project - it works fine through the SignalTapII. I tried to remove the last added module from my project and after few compilation, resetting the programmer, the board and my computer, the MAX10 started working. I put the missing module back and continued my work, tracing the operation. After about 10 traces SignalTapII didn't capture the complete trace (about 25% of the samples) and after I tried to reset the MAX10 chip and download the program I got the same message "Invalid JTAG configuration".   Please help!  Thank you.

[Altera_Forum]

Based on your description it sounds like power supply issue. Module that you're referring to might be disrupting the power to MAX10 rendering JTAG failure.

[Altera_Forum]

I solved the problem - it is CONF_DONE, pin 138. I used it as an option pin for debugging and when I strapped it to Gnd, the MAX10 chip stopped working. Once the jumper is removed, everything is OK. 

 In the Quartus dialog Assigments->Device->Device andPinsOptions->General there is a check box "Enable nCONFIG, nSTATUS, and CONF_DONE pins". I understood that by un-checking the check box I will be able to use any of these pins as regular inputs. It turns out that tying CONF_DONE to Gnd prevents the MAX10 device from entering user mode regardless of the state of the check box!  The description of the check box in the dialog reads: "Enables major configuration pins, nCONFIG, nSTATUS, and CONF_DONE pin in user mode. If this option is turned off, the nCONFIG, nSTATUS, and CONF_DONE pins are disabled when the device operates in user mode and is available as a user I/O pin." I think there is a bit of ambiguity here because if the CONF_DONE intended to be used as an input and that input is low (tied to Gnd) the part will not enter user mode. I feel it would help users if Altera clarify that.

[Altera_Forum]

--- Quote Start ---  Based on your description it sounds like power supply issue. Module that you're referring to might be disrupting the power to MAX10 rendering JTAG failure.  --- Quote End ---   jackyb0i, thank you for you thought. The power supply was OK. It is actually CONF_DONE pin strapping to Gnd.

[Altera_Forum]

--- Quote Start ---  I solved the problem - it is CONF_DONE, pin 138. I used it as an option pin for debugging and when I strapped it to Gnd, the MAX10 chip stopped working. Once the jumper is removed, everything is OK.  In the Quartus dialog Assigments->Device->Device andPinsOptions->General there is a check box "Enable nCONFIG, nSTATUS, and CONF_DONE pins". I understood that by un-checking the check box I will be able to use any of these pins as regular inputs. It turns out that tying CONF_DONE to Gnd prevents the MAX10 device from entering user mode regardless of the state of the check box!  The description of the check box in the dialog reads: "Enables major configuration pins, nCONFIG, nSTATUS, and CONF_DONE pin in user mode. If this option is turned off, the nCONFIG, nSTATUS, and CONF_DONE pins are disabled when the device operates in user mode and is available as a user I/O pin." I think there is a bit of ambiguity here because if the CONF_DONE intended to be used as an input and that input is low (tied to Gnd) the part will not enter user mode. I feel it would help users if Altera clarify that.  --- Quote End ---    Vgelman,   The pins are dual purpose and can be used in user mode. But you have to account for what happens before the device can enter user mode: configuration mode. The configuration pins(nconfig, nstatus and conf_done) need to be pulled high for successful configuration. A high CONF_DONE usually signify a successful configuration. The FPGA can't tell if the configuration is successful if the CONF_DONE does not go high. In your case the FPGA will always think that it is still in configuration mode since CONF_DONE is tied to ground. If you want CONF_DONE to be low, you can set it to GPIO low, in which the changes will take effect once you enter user mode. Cheers :)