Invalid logic levels at output of FPGA

[Altera_Forum]

Hi,  

 I've written a code for a state machine in an EP3C10F256 FPGA. I program the FPGA successfully but two of the FPGA outputs which correspond to two bits from a 16-bit register no not stand at any logic levels and they fluctuate somewhat like a mid-rail random sine wave with a low amplitude. I thought maybe the FPGA has a problem so I changed the pin assignment to a pin which was working moments before but got the same result.  The worst part is that when I'm trying to simulate the design Quartus freezes! (I'm not sure if this is the right place to also pose this problem but I'm not sure if it could also be a sign that there's something wrong with the code and it's implementation). The code is posted below: I'm looking at the outputs of the variable named "TimeCont".     module PixelTiming( clk,  restart, Decoder_Staggered, Sample, Shutter, GlobRST, GlobRST_Enable, TimeCont, error );     input clk; input restart;   output [0:7] Decoder_Staggered; output Sample; output Shutter; output GlobRST; output GlobRST_Enable; output error;  output [0:15] TimeCont;   reg [7:0] Decoder_Staggered = 8'b00000000; reg Sample; reg Shutter; reg GlobRST; reg GlobRST_Enable;   reg [1:0] state = 2'b11; reg [1:0] nextstate; reg [15:0] timer = 0; reg error = 1'b1;    wire [0:15] TimeCont = timer;          // ------------------------------------------------------------------------------------------------ // Time Parameters for 40MHz Clock => 25ns period    parameter T_init = 40 ;   parameter T_RowOn = 16'h0BB8 ;   parameter T_Pulse = 40 ;   parameter T_Column = 16'h0BB8 ;    parameter T_conversion = 16'h05DC ;     parameter S_Int = 2'b00;  parameter S_Conv = 2'b01;  parameter S_Reset = 2'b10;  parameter S_HARD_RESET = 2'b11;       always @(posedge clk) begin    if (restart == 0)  state <= S_HARD_RESET ;    else       state <= nextstate;     end   always @* begin      case(state)      S_HARD_RESET: begin    timer <=0;   nextstate = S_Int;    end     S_Int: begin      if (timer == T_Pulse) begin  GlobRST_Enable <= 1'b0;  GlobRST <= 1'b0;  Decoder_Staggered <= 8'h00;  nextstate = S_Conv;  timer <= 0;  end    else begin  timer <= timer + 1;  Sample <= 1'b0; //All pixels have rolling mode of operation  Shutter <= 1'b1;    GlobRST_Enable <= 1'b1;  GlobRST <= 1'b1;  Decoder_Staggered <= 8'hFF;  end    end      S_Conv: begin    if (timer == T_Column) begin  nextstate = S_Reset;  timer <= 0;  end  else  timer <= timer + 1;    end      S_Reset: begin    if (timer == T_Pulse) begin  nextstate = S_Conv;  GlobRST <= 1'b0;  Decoder_Staggered <= Decoder_Staggered + 1'b1;  timer <= 0;  end    else begin  timer <= timer + 1;  GlobRST <= 1'b1;  end     end    default: begin  nextstate = S_HARD_RESET;  end    endcase end       endmodule

[Altera_Forum]

Your problem is you have your timer free running and not based on clock. 

 You have mixed your state machine logic and other logic together.. And have the timer addition happening regardless in a combinational block instead of a clock based always block.   so in simulation the timer is just free running and zero time is moving forward, thus the "Hang" you are experiencing.  On the hardware, the timer is running like mad at the highest combinational frequency that is possible, so the output looks like a sign wave because it's toggling faster than the output can really reach.   Isolate the statemachine case from the logic case, and move the logic case into a always@(posedge clk) block and you should be closer.  Pete