- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I was trying to use Generic Serial Flash IP from Quartus Standard 23.1.1 to access S25FL127S using QUAD I/O command (i.e. address and data sent over SPIx4). It works some of the time but not always. This is my configuration (I'm using Standard so I had to write my own driver):
// Set 25MHz clock. The Flash allows up to 80MHz.
FLASH_IORW_32(FLASH_REG_BAUD, 0x1);
// Use the QUAD IO Read command with 6 dummy cycles. This is actually
// 2 cycles for the mode and 4 dummy cycles.
FLASH_IORW_32(FLASH_REG_READ, (6 << | 0xeb);
// Send the data and address over SPIx4.
FLASH_IORW_32(FLASH_REG_PROTOCOL, (0x2 << 16) | (0x2 << 12));
The actual command requires (as configured above)
- 0xEB to be send over SPIx1
- Then the address to be sent over SPIx4.
- Then a mode byte is sent in 2 cycles over SPIx4.
- Then 4 dummy cycles are issued where data sent/received is ignored.
- Then the data to be read over SPIx4.
If the first nibble of the mode byte is 0xA then the flash assumes that the next command is a QUAD I/O read and does not expect the command to be sent on the next operation.
To get the Generic Serial Flash IP to work I essentially just configured 6 dummy cycles. The problem is that the value output during the dummy cycles seems to depend on the address of the last operation. The value output during the dummy cycles seems to be the second nibble of the last address:
// This read may or may not work depending on what happened before.
alt_u32 val1 = __builtin_ldwio((void*)0xf000b0);
//For this read 0xb will be output during the dummy cycles. This read
// works.
alt_u32 val2 = __builtin_ldwio((void*)0xf000a0);
//For this read 0xa will be output during the dummy cycles. This will
//interpreted by the S25FL127S as meaning the *next* read will just have
//address & dummy cycles, that is, no command needs to be sent. This read
//works.
alt_u32 val3 = __builtin_ldwio((void*)0xf000b0);
//This read fails because this sends a command but
//the flash is only expecting an address and dummy cycles because
//of the previous read.
alt_u32 val4 = __builtin_ldwio((void*)0xf000c0);
You can see this below which shows the reading of val3. The first mark shows the first address nibble (in dout). The second mark shows how 0xA is output in the first dummy cycle (i.e. mode) (in dout). The third mark is the data being returned (in din).
Is it actually possible to use the Generic Serial Flash IP when a mode is included in the operation? To make the IP work I had to configure 6 dummy cycles (+2 for the mode and +4 for the dummy cycles). Is there a way to fix the value output during dummy cycles?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.
Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.
We appreciate your patience and understanding, and we are committed to providing you with the best support possible.
Thank you for your understanding.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Yes GSFI IP can work with Quad I/O mode as mention the userguide.
What is the FPGA device that was used?
Regards,
Aiman
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It is a Cyclone V (5CSXFC6D6F31C6N).
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I just check that S25FL127S was not tested and not confirm to work from our end. The error might be due to the flash is not compatible with the FPGA. You may see the 3rd party configuration devices list for Cyclone V below:
Regards,
Aiman
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page