Is every module need a reset signal?

[Altera_Forum]

in the timing diagram ,data0,data1,data2,data3 are the input data for the ram ,and there are output data,we,oe2 is the write and read signal respectly? but there is no reset signal? I wonder how the addr can be reset,since there is no reset signal . Anybody knows?

[Altera_Forum]

Usually you don't need to reset the input signal to a RAM (or any other digital circuit). 

Just change it when needed.  If you don't want to carry any more read operations use the signals that enables and disable the whole memory.

[Altera_Forum]

I mean how the address of the ram can be generated,since there is no reset signal,how could i get the addr reset on start?

[Altera_Forum]

I am not sure what you are actually referring to but it is you, the designer, who should generate the address as required.

[Altera_Forum]

--- Quote Start ---  I mean how the address of the ram can be generated,since there is no reset signal,how could i get the addr reset on start?  --- Quote End ---    Sorry but I don't understand your question. Why don't you try providing a more detailed description of what you want to do?  Whic FPGA you want to use, is the RAM internal or external, which RAM are you using, to do what, etc.

[Altera_Forum]

I mean the addr should be 0,1,2,3..... 

but there is no reset signal ,which signal could i use to determine the addr 0? when i have reset signal,i can set addr to 0 when the reset is low.So what can i do?

[Altera_Forum]

The memory address is not generated by the memory. It is generated by some external circuitry... a processor, or maybe a counter or something. You would reset the processor or counter to start generating addresses at '0'. Those have reset inputs.

[Altera_Forum]

NO,this module contains a ram and a control circuit,so it is generated by this module.

[Altera_Forum]

--- Quote Start ---  this module contains a ram and a control circuit  --- Quote End ---   Unfortunately you didn't provide any information about operation and intended purpose of "this module". Possibly it relies on FPGA power on reset, but yes, in many cases it's better to have an explicite reset for reliable operation.

[Altera_Forum]

Either:  

 1) it is a ram (random access memory), meaning you have external access to the memory address lines (in which case your external control of these lines is what needs to be reset, not the ram),   Or:   2) it is not a ram (and you need to ask a more precise question).