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Altera_Forum
Honored Contributor I
780 Views

Is it possible to implement async ROM/RAM in Stratix family?

Hi, 

 

I need to have an asynchronous RAM/ROM in Cyclone IV E for my MIPS processor. Unfortunately, Stratix device family does not support LPM_ROM or LPM_RAM_DQ without providing the inclock/outclock of the units. Any way to go around this limitation? 

 

Currently, I have made a custom ROM/RAM with array and std_logic_vector but I don't know how to initialize them outside of (OTHERS (OTHERS => '0'))
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5 Replies
Altera_Forum
Honored Contributor I
37 Views

The problem is, any build in RAMs in FPGAs are synchronous, so Asynchronous ram will need to be built from logic. Are you really after a fully async ram, or just on the read side?  

Have you tried looking at the synthesis templates for inferred rom/ram? What version of quartus are you running? 

 

Quartus should allow initialisation of the ROM using any constant or function call, eg: 

 

type rom_t is array(0 to 255) of std_logic_vector(7 downto 0); function init_rom return rom_t is variable r : rom_t; begin for i in r'range loop r(i) := std_logic_vector( to_unsigned( i, 8) ); end loop; return r; end function constant rom : rom_t := init_rom;
Altera_Forum
Honored Contributor I
37 Views

>Are you really after a fully async ram, or just on the read side? 

 

It's a single clock cycle processor, is async ram a bad design?
Altera_Forum
Honored Contributor I
37 Views

Hello all,  

 

I want to ask about the global and local interconnections in Stratix. In which case I can use almost 100% of the interconnections? I run multiple designs on stratix FPGA, and sometimes the running fails because of either global and local interconnections limitation, however, when I read the reports it say less than 50% in both of them.  

I want to understand how interconnections are used in FPGA, if you can help either sending me the links or any suggestions I would appreciate it! 

 

Thanks
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

>Are you really after a fully async ram, or just on the read side? 

 

It's a single clock cycle processor, is async ram a bad design? 

--- Quote End ---  

 

 

It will really depend. Internal rams can do asynchronous read, but long path delays are going to decrease the maximum clock frequency possible. Synchronous is always better as it will always shorten the paths and increase the max frequency.
Altera_Forum
Honored Contributor I
37 Views

 

--- Quote Start ---  

Hello all,  

 

I want to ask about the global and local interconnections in Stratix. In which case I can use almost 100% of the interconnections? I run multiple designs on stratix FPGA, and sometimes the running fails because of either global and local interconnections limitation, however, when I read the reports it say less than 50% in both of them.  

I want to understand how interconnections are used in FPGA, if you can help either sending me the links or any suggestions I would appreciate it! 

 

Thanks 

--- Quote End ---  

 

 

Rather than hijacking someone elses thread, I highly suggest you start your own thread where people are more likely to see it.
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