We are designing a board in which we would like not to use the analog features, like PLL, VCO and ADCs of a MAX10. UG-M10CLKPLL par. 2.3.6 states : "The only time that the VCO is completely disabled is when
you do not have a PLL instantiated in your design". Does it mean that whitout instantiations of a PLL in the design we can assume that all the VCO are powered down? Do we also need to connect to GND the AVDD?
PLL unused pins can be connected to GND. Ref page no:4
And please note, if you are not using the analog feature in Max 10, still needed power to these blocks by VCCA. and VCCD_PLL Page no:15
But, if you using the PLL IP, the whole PLL IP block will not be used.
But cannot say the power to VCO is completely cutoff.