Hello,
I have to write a VHDL code in which i wrote case statement two times for the same FSM states(case statement was in fact interrupted by an if statement).Please look at the underlined lines of the code to understand what i mean.
case etat_courant is
when Idle =>
SCLK<= '1';
SDIN<= '1';
if SDIN = '0' then etat_suivant<= Start_recep;
end if;
when Start_recep =>
SCLK<= '1';
SDIN<= '0';
if SDIN = '1' then etat_suivant<= Reception;
end if;
when Reception =>
if (m <= 47) then
if (s <= 7) then
--while (m <= 47) loop
--while (s <= 7) loop
SDIN<= ADCDAT(s);
s:= s+1;
--end loop ;
end if ;
m:= m+1;
--end loop ;
elsif (m = 48) then etat_suivant<= Depart_trans;
end if;
end case;
if (n <= 15) then
case etat_courant is
when Depart_trans =>
SCLK<= '0';
SDIN<= '0';
if (SDIN = '1') then etat_suivant<= Tran_addr;
end if;
when Tran_addr =>
if (i < 7 ) then
SDIN<= adr_reg (i);
i:= i+1;
--end loop ;
DATA_0<= adr_reg & '0';
elsif (i = 7) then etat_suivant<= Ack_1;
end if;
when Ack_1 =>
SDIN<= '0';
ACK<='1';
etat_suivant<= Trans_data_1 ;
when Trans_data_1 =>
ACK<='0';
if (j < 8 ) then
SDIN<= DATA_1(j);
j:= j+1;
elsif (j = 8) then etat_suivant<= Ack_2;
end if;
when Ack_2 =>
SDIN<= '0';
ACK<='1';
etat_suivant<= Trans_data_2 ;
when Trans_data_2 =>
ACK<='0';
if (k < 8 ) then
SDIN<= DATA_2(k);
k:= k+1;
--end loop ;
elsif (k = 8) then etat_suivant<= Ack_3;
end if;
when Ack_3 =>
SDIN<= '0';
ACK<='1';
etat_suivant<= Stop_cond_1 ;
when Stop_cond_1 =>
ACK <= '0';
SDIN<= '0';
SCLK<='0';
etat_suivant<= Stop_cond_2 ;
when Stop_cond_2 =>
SDIN<= '0';
SCLK<='1';
etat_suivant<= Stop_cond_3 ;
when Stop_cond_3 =>
SDIN<= '1';
SCLK<='1';
etat_suivant<= Depart_trans ;
when OTHERS =>
etat_suivant<=Idle;
n:=n+1;
end case;
elsif ( n > 15) then
fin<='1';
etat_suivant<= Idle ;
end if;
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4 回复数
No it's not this what i need.I want to have the states within if statement looped together for 16 times on a row.
Take a look at this FSM schematic: https://www.alteraforum.com/forum/attachment.php?attachmentid=1284
From what I see in your schematic you can put the if statement inside the Stop_Cond_3 state.
You should also initialize all your variables somewhere. I guess setting them to 0 in the Idle state should do the trick.I think, the shown code isn't legal VHDL because each case statement must either cover all possible state alternatives or contain an others case. It's no problem to supplement the code respectively, but the design is at least rather confusing. Thus I would also suggest to merge the code into one case statement.
