Is my CycloneIV Configuration Circuit correct?

[Altera_Forum]

Hi guys, 

 currently I´m planning a board, with a Cyclone IV: EP4CE6E22C8. Till now I am working with a De0nano Dev-Board, now I want to make my own.  I´m not sure, if I have connected the USB-Blaster and the Flash memory correctly. Can you check my circuit please?  I want to be able to configure the FPGA over JTAG and I also want to configure the flash indirect via JTAG. I´ve used some informations from datasheets and the De0nano schematics. But I´m not sure, if everything is correct.  Are there some errors or could something be better?  I know, at the moment the 50MHz Oszillator is missing.  Greets Olaf

[Altera_Forum]

You have duplicate pull-up resistors on TDI - I suspect one was intended for TMS. 

 Your MSEL setting is wrong. You've selected Active parallel. You need to set the pins to "010" for standard Active serial mode. Devices without MSEL3 don't support fast AS configuration mode - if that's what you'd intended.  Everything else is fine.  Cheers, Alex

[Altera_Forum]

2crabtack 

Check my circuit here http://www.alteraforum.com/forum/showthread.php?t=50759 100% working (JTAG, AS). Idk if it is ok for indirect.

[Altera_Forum]

Hi, thank you for your answer! 

 You´re right, it hast to be "010" for selecting Active Serial.  But now I don´t understand, why the DE0 NANO Board use 101, see Attachment.  Greets  Olaf

[Altera_Forum]

strange this de nano this is behave in inverted mode? should not be

[Altera_Forum]

--- Quote Start ---  Smaller Cyclone IV E devices or package options (E144 and F256 packages) do not have the MSEL[3]pin. The AS Fast POR configuration scheme at 3.0- or 2.5-V configuration voltage standard and the AP configuration scheme are not supported in Cyclone IV E devices without the MSEL[3]pin.  --- Quote End ---  Although it states AS Fast POR isn't supported without MSEL3, AP isn't either. So, it certainly appears not to be covered in the documentation. However, it clearly works. Whether you get a 'Fast' or 'Standard' POR delay is probably anyone's guess.  Despite the Nano design example, I recommend you follow the docs. I have a Cyclone IV design in front of me that does just that - it works perfectly. I think it somewhat foolish of Altera/Terasic to release a board, which will clearly be used as a reference design, with an apparently(*) undocumented configuration scheme.  Cheers, Alex  (*) Perhaps it is covered, but I can't find it...!