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Altera_Forum
Honored Contributor I
959 Views

Is "phase shift" or "delay" a constant whatever the frequency is?

Hello, 

 

I'm working on a DE0-Nano and I'm trying to control the SDRAM chip located one DE0 board.  

After reading a few tutorial, it seems DRAM_CLK signal needs to lead by 3 ns other SDRAM signals.  

It is said that "the clock skew depends on physical characteristics of the DE0-Nano board" and that "it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds". (source -> ftp://ftp.altera.com/up/pub/altera_material/11.0/tutorials/vhdl/de0-nano/using_the_sdram.pdf, chapter 7 - p11) 

 

My question is: 

Is that delay a constant whatever clock frequency is? 

Othewrwise, I guess the phase shift needs to be kept as a constant.  

 

So in the control of my PLL should I specify: 

-> phase shift = -54 deg (then delay = 3ns@50MHz, 1.5ns@100MHz, 1.05ns@143MHz) 

OR 

-> clock delay = 3 ns (then phase shift = -54deg@50MHz, -108deg@100MHz, -154.4deg@143MHz) 

 

If anyone also know the physical reasons, I would be please to hear it. 

 

Thanks for you help, 

 

Jean
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Altera_Forum
Honored Contributor I
56 Views

That's a really old document you are referencing. Are you using a newer version of the software? If so, the controller IP should handle this.

Altera_Forum
Honored Contributor I
56 Views

Thanks for your reply sstrell, 

I'm using latest version of Quartus Lite but still need version 14SP1 to use the MegaWizzard Function Plugin. 

The puprose of my project is to design a RAM controller so I need to specify timing constraints on RAM ports in order to make sure ISSI_SDRAM timing are met. 

I had a look to a lot of document and the mentioned document is the only one to specify that delay. Unfortunately, the value is given at 50MHz and nothing is said about higher frequency (DRAM datasheet only specify 2 working frequence: 100MHz and 143MHz and I decided to go for 143MHz). 

I would like to understand the reason of that delay. If it is because the wire is long and the signal then needs more time to reach registers inside the DRAM or if new clocks are generated inside the DRAM but a fix delay of 3ns can be observed.....:-s Probably something else?  

 

Do you know more than me about that requirement? 

 

Thanks, 

 

Jean
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