Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
937 Views

Is there a standard way for an FPGA Qsys system (Nios II) to access HPS pins?

Is there a standard method to connect FPGA side Qsys system Nios II to HPS pins and disable the HPS access to them? This needs to be done for UART, GPIO and Pushbuttons for Cyclone V SoC on the DE10-Nano board for experimental purpose at this time.

0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
97 Views

Yes. Boot the processor. 

 

You can configure in Qsys the pins for LoanIO. If you want to use the pins as inputs you don't need the processor running as the pins default to input. However to use them as outputs (e.g. UART TX) you will need the processor up and running as it has to configure internal mux registers to allow the LoanIO interface to control the pins.
Altera_Forum
Honored Contributor I
97 Views

Is it sufficient to have preloader and not a user program runnign in the HPS i.e not "go all the way"?

Altera_Forum
Honored Contributor I
97 Views

Preloader has to run. If you modify the preloader to sit in an infinite loop at the end rather than loading an image (and set BSP with watchdog disabled), you should be fine.

VROGE2
New Contributor I
97 Views

I am new to the DE10-nano and I am trying to use the UART TX pin as an output. I came across this thread as I was searching for a way to do this. What is meant by Boot the processor? and how does one configure the pins for LoanIO?

 

Thanks

Reply