Is there a way to specify a wire inside FPGA?

[Altera_Forum]

Hi All, 

 I have an I2C board that outputs GND, SCL and SDA for I2C implementation.  I need the SCL and SDA I2C signals, including the bi-directional SDA to go through a Cyclone III FPGA from two ports to two other ports.  Is there a way to specify something like the "tranif" verilog component in the FPGA so that two inout pins can be connected by a wire that can carry signals bi-directionally?  Thanks,  RAUL

[Altera_Forum]

I think no. I'd tryed to do it on MAXII CPLD, it doesn't work. You should explicitly control tri-state IO.

[Altera_Forum]

You can answer the question yourself by considering the nature of a bidirectional open drain signals as SDA and SCL. You may want to study the operation of dedicated bidirectional I2C buffers available from Philips/NXP. They basically require special hardware to derive a direction signal. This kind of hardware is not present with any Altera or other vendors FPGA. 

 In some special cases, you are possibly able to derive the direction information from watching the protocol. In external hardware, if no level translation or buffering is required, a bus switch will do.

[Altera_Forum]

Provided you don't try to connect your signal in a higher level module, you can drive an inout signal down to a lower module. 

 However normal practice is to do I/O driving in the top level, driving data and output enable signals as outputs to the top level and sending signals down to the inner levels.   example:  inout pad_sda; inout pad_scl;  wire sda_oe_n; wire scl_oe_n;   assign pad_sda = sda_oe_n ? 1'b0 : 1'bz; assign pad_scl = scl_oe_n ? 1'b0 : 1'bz;   i2c_module i2c_inst (  .sda( pad_sda ),  .sda_oe_n( sda_oe_n ),  .scl_oe_n(scl_oe_n )  );   then in   module i2c_module (  sda,  sda_oe_n,  scl_oe_n );  input sda; output sda_oe_n; output scl_oe_n;  ....  endmodule

[Altera_Forum]

Thanks guys, I was going to try ALTDDIO_BIDIR but I saw that it was not just a bi-directional pass transistor. 

 I will have to physically connect the signals on the board on a bus outside of the FPGA.  RAUL

[Altera_Forum]

I just read your first post again (d'oh) and realised that what you're trying to do is create an I2C repeater. 

 As FvM says, you can't do this, without decoding the protocol inside the FPGA and creating an active bridge. Even that is tricky, given the nature of the bus.   However, I'm wondering why you need to do this. Can you elaborate ?

[Altera_Forum]

Hi Again, 

 I am trying to control, via I2C, a device attached to one of the Santa Cruz ports of an SLS HSMC-to-Santa Cruz converter board. The device's I2C ports are attached to GPIOs of the Santa Cruz board.  RAUL

[Altera_Forum]

I had a suspicion you were trying to do something like this. 

 I2C is a multimaster bus. You can just attach your SCL/SDA lines to the device at the same time as the Santa Cruz board.   Your code can either act as an I2C passive bus monitor, or can jump in and drive the lines. I2C is only driven low and relies on external pullups so there is not a problem with bus conflict.  The only problem would be if the Santa Cruz board is not a well-behaved master, in which case it might not behave well if your code accesses the device at the same time as it does.

[Altera_Forum]

Fortunately the device I am trying to control is only an I2C slave, so directly soldering headers to the Santa Cruz device board should allow me to control the device. 

Thanks.