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Altera_Forum
Honored Contributor I
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Issue Configuring MAX10: "Can't Access JTAG Chain"

Hey all, 

 

I'm trying to configure a MAX 10 on a custom PCB (it's the 10M08SCE144C8G--same FPGA as on one of the altera evaluation boards (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-max-10-evaluation.html)), but I'm having JTAG issues. I'm using Quartus 16.1 Lite and the teraisic USB-Blaster, and I'm not having luck loading either the POF or SOF files. If I try to load the SOF file, I get a "Can't access JTAG chain" error; if I try to load the POF file, I get a JTAG error code 35 error. 

 

On the PCB, the pinouts seem OK (schematic attached..please note that "VCCA" is the single 3.3V supply fed to all of the FPGA's power pins). The design is based off the evaluation board schematics. After testing w/o success, I went back and added 10pF capacitors to GND and Schottky diodes to VCCA for TCK, TDO, TMS, and TDI (as recommended in the MAX10 Configuration User Guide), but this did not fix it.  

 

I probed the JTAG header on my board with a 1GHz/ 5GSa/s Agilent scope and got the following screen shots. This are triggered for when I clicked "Start" to program the board. Not pictured is TMS, which appeared to be changing states--I can include a snapshot tomorrow if helpful.  

 

I also probed the power pin and it appears to meet the power up requirements. It rose to full voltage in 500ns vs the <10ms requirement. I saw that the NSTATUS pin goes high as expected from the Configuration manual. 

 

A few concerns: 

 

 

 

Any thoughts would be greatly appreciated! Let me know if you have any other questions. 

-J
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Altera_Forum
Honored Contributor I
95 Views

For anyone reading this, I've resolved the problem. 

 

The issue was that there were unsoldered pins. With this package of IC (QFP-144), it can be difficult to tell if pins are soldered visually. Instead, you can gently press on each pin with a fine-tipped tool (e.g. exacto knife) while observing it under a microscope. If you notice the pin wiggle, it's not properly attached.  

 

Other recommendations: While debugging this problem, I did find that my configuration pins were not properly set up. This is partly due to my own mistakes amplified by inconsistent/ambiguous documentation (this isn't so much a critique as it is an acknowledgement that FPGAs are extremely and many legitimate configurations exist).  

 

For the MAX10 devices, I highly recommend the MAX 10 Design Guidelines Document (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/m10_guidelines....). Use this early and often when you're designing your system! 

 

Cheers, 

J
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