Issue in Micron NOR Flash Memory (MT25QU01GBBB) Write/Read using Generic Serial Flash Interface

[SindhuParvathi]

Issue in Micron flash memory (MT25QU01GBBB ) write/read through QSPI interface using Generic Serial Flash Interface 

1. In default Single IO mode, data written to the memory is different from the data read from a location

Ex: master_write_32 0x00000000 0x1234ABCD

      master_read_32 0x00000000 0x000000f0 

2. Able to read device id (0x1021bb20 )

3. Not able to change micron flash memory to Quad I/O Mode, tried changing the mode by writing to both volatile and non volatile configuration register.

Operating Clock : 100MHz

SPI Clock Baud Rate Divisor : /32 (default value)

Script used for write/read:

Write Memory:

Write Enable (06h)

Chip Select delay : 5 (as mentioned in GSFI UG for 100MHz)

Operating Protocol Register : 0x00000000 

Control Register : 0x00000101

Write Instruction : 0x00007002

master_write_32  0x00000000 0x1234ABCD

Status Register Values:

Status Register : 0x00000000

Flag Status Register : 0x00000081 

Non Volatile Configuration Register : 0x0000ffff

Enhanced Volatile Configuration Register : 0x000000ff

Read Memory:

Operating Protocol Register : 0x00000000 

Control Register : 0x00000101

Read Instruction : 0x00000403

master_read_32 0x00000000

Using the Reference Quartus Design from Generic Serial Flash Interface User Guide - Flash Access Using the Generic Serial Flash Interface Intel FPGA IP Section 

[NurAiman_M_Intel]

Hi,

Thank you for contacting Intel community.

1. What is the FPGA device that was used?
2. What is the Quartus version that was used? Quartus Pro 21.2? Quartus standard 20.1?

Regards,

Aiman

[SindhuParvathi]

Hi Aiman,

Thanks for the Response

1. FPGA device used is Arria 10 (10AS066N3F40)

2. Quartus Pro 20.2

3. QSPI Boot Flash card provided with A10 SoC Dev Kit is used (Micron NOR Flash Memory MT25QU01GBBB)

Able to Read and Write to the flash memory in default SPI mode - 4 byte addressing mode by

• Erasing Sector before writing
• Adding delay (1s) after write operation.

But unable to change the flash memory mode to Quad I/O. Tried to write enhanced volatile, volatile and non volatile registers - registers values did not change from default value

Following are the steps followed to Enable in Quad mode using Enhanced Volatile Register

1. Enter Quad IO Mode (35h)

Observation: after writing this opcode to the flash memory register, all the values (Device ID, Enhanced Volatile Register) are set to 0x0000 0000. Not able to proceed after this. Resolved only after power ON

2. Write Enable (06h)

3.Write Enhanced Volatile Configuration Register (06h) -Writing 0x0000007F to the register (7th bit set as 0 to Enable Quad Mode)

4. Read Enhanced Volatile Configuration Register (65h)

Following are the steps followed to Enable in Quad mode using Non  Volatile Register

1. Write Enable (06h)

2. Write Non Volatile Configuration Register (B1h) -Writing 0x0000FFF2 to the register (Enable Quad Mode)

Observation: after writing this register, all the values (Device ID, Non Volatile Register) are set to 0x0000 0000.

3. Power ON (to reset flash device)

Observation: even after power ON the register value is not changed from 0x0000 FFFF

4. Read Non Volatile Configuration Register (B5h)

Don't know reason for the device id to reset as 0x00000000 after register write

Is the sequence in the above two procedures correct? If not, what is the correct sequence?

How to Read/Write in Quad SPI Mode and perform flash read/write in burst mode?

Note: All the opcodes and scripts referred from GSFI IP User Guide  

Regards,

Sindhu Parvathi

[SindhuParvathi]

Hi Aiman,

Adding points and snapshots related to query posted above

Script used for Enter Quad IO Mode :

proc enter_quad_io_mode {} {
global mp operating_protocols_setting flash_cmd_setting flash_cmd_ctrl flash_cmd_write_data_0

#read data and address set to quad IO mode in GSFI IP
master_write_32 $mp $operating_protocols_setting 0x00022000

#quad mode - Micron NOR Flash Opcode
master_write_32 $mp $flash_cmd_setting  0x00000035
master_write_32 $mp $flash_cmd_ctrl 0x1
}

Observation: After the enter_quad_io_mode commands are executed Device ID Read and status registers value is 0x00000000

Script used for Write Enhanced Volatile Configuration Register :

proc write_evcr_quad {} {
global mp flash_cmd_setting flash_cmd_write_data_0 flash_cmd_ctrl
master_write_32 $mp $flash_cmd_setting 0x00001061
master_write_32 $mp $flash_cmd_ctrl 0x1

#Set to 7F for Quad Mode in Flash Memory, default value is FF
master_write_32 $mp $flash_cmd_write_data_0 0x0000007F

}

Script used for Read Enhanced Volatile Configuration Register :

proc read_evcr {} {
global mp flash_cmd_setting flash_cmd_ctrl flash_cmd_read_data_0

master_write_32 $mp $flash_cmd_setting 0x00001865
master_write_32 $mp $flash_cmd_ctrl 0x1
set status_register [master_read_32 $mp $flash_cmd_read_data_0 1]
puts "Read Enhanced Volatile Configuration register : $status_register"
return 0
}

Note: Not sure if the order of the commands used is creating the issue. 

Attached the snapshot of the script results (System Console)

[NurAiman_M_Intel]

Hi,

Thank for your reply.

Did you follow the steps to perform writing to memory device using QUAD SPI mode from below link in page 32 correctly? Or is there any changes?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf (page 32)

Regards,

Aiman

[NurAiman_M_Intel]

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