Issue with updating ARIA 10 PCIe core to 20_1_1

[mwf]

We are migrating to a new hardware design server and are converting existing FPGA designs from Quartus 17.1 to Quartus 22.3. We have a number of PCIe Gen 3 x 8 designs that build without issue and run fine on the hardware. This is with both Quartus 17.1 and 22.3. Using 22.3 requires an update of the PCIe core to 20_1_1. This core works fine when configured as Gen 3 x 8.

We also have a number of PCIe Gen 2 x 8 designs. They all work fine when built with Quartus 17.1. But the first design I tried builds with 22.3 but doesn't work on the hardware. I get various errors including PC hangs, no access to PIO slave registers, and DMA failures from our FPGA to host (PC) memory.  Changing seeds changes behavior slightly. 

I also tried Quartus 19.2 which has an optional PCIe core update to 19_1. This core appears to work fine when configured as Gen 2 x 8.

The PCIe core and a lot of our IP run at 250Mhz. There are no timing errors reported by either Quartus version.

Thanks for any ideas,

Mike

[Wincent_Altera]

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