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Hello,
Does anyone have guidelines as to how the fPLL's inputs and outputs are to be connected to the logic? I have been unable to get hold of a proper method for a very long time. Board: Arrow SoCkit Evaluation board. Cyclone V 5CSXFC6D631C6 Here is a sample top level file: module top( input clk, input rst, input driver_clk, output pll_out, output locked_port, output data ); driver d1( .clk(driver_clk), .rst(rst), .data_out(data) ); pll pll_inst ( .refclk (clk), // refclk.clk .rst (rst), // reset.reset .outclk_0 (pll_out), // outclk0.clk .locked (locked_port) // locked.export ); endmodule If someone could provide the pin numbers for the clk, driver_clk and pll_out, it would be much helpful Thanks for your time.Link Copied
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