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Questions on PCIE communication protocol implementation in RIFFA

Honored Contributor II

I am using Riffa PCIE coding in Altera DE4 



1) According to the completion TLP in , why allocated 12 bits and 8 bits for data and header respectively ?  


2) For , why " Note that data on chnl_rx_data may begin to arrive before chnl_rx_ack is pulsed, but the fifo will never overflow. " ? 


3) Why and using different number and types of FIFO ?
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