I am trying out JESD IP example design to test in loopback mode, I generated design from Quartus prime pro 23.4
I am aware of the fact that only GX device is available in the dropdown list while generating the JESD IP example design. So, I generated the ED with board as NONE and later modified the pin constraints as per the SX device.
Design changes made wrt SX SOC devkit PRD edition :
1. Jesd IP configs are left at default settings except only refclk frequency changed to 100MHz from 125MHz in order to facilitate the clock from onboard SI clock chip.
2. global_rst_n pin is assigned to user push button - R5 pin - FPGAIO2_P net name.
3.SPI pins are assigned as Virtual pins.
4. sma_clk_out pin is set as virtual pin (This pin was just clock forwarded from device_clk in design)
5. Rest all pins are mapped accordingly to FMCB slot and loopback card is plugged into FMCB slot.
Design is going through till assembler without any errors, but facing issue while running through system console - Stuck at waiting for reset active low in system console.
Any inputs and help very much appreciated. Thanks
Sequence followed :
1.Board power ON -> Program SOF(100% succesfull) -> Launch system console -> Load sof
Modified -> main.tcl -> set master_index [expr {$master_list_length - 2}]
Rest of the steps I am following as per the user guide, I have attached the snap of the same.
QSF I have attached below :
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AS066N3F40E2SG
set_global_assignment -name TOP_LEVEL_ENTITY altera_jesd204_ed_RX_TX
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data[1]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to rx_serial_data[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to rx_serial_data[1]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to tx_serial_data[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 0_9V -to tx_serial_data[1]
set_location_assignment PIN_Y31 -to rx_serial_data[0]
set_location_assignment PIN_Y30 -to "rx_serial_data[0](n)"
set_location_assignment PIN_W33 -to rx_serial_data[1]
set_location_assignment PIN_W32 -to "rx_serial_data[1](n)"
set_location_assignment PIN_W37 -to tx_serial_data[0]
set_location_assignment PIN_W36 -to "tx_serial_data[0](n)"
set_location_assignment PIN_V39 -to tx_serial_data[1]
set_location_assignment PIN_V38 -to tx_serial_data[1](n)"
#100MHz mgmt clk
set_instance_assignment -name IO_STANDARD LVDS -to mgmt_clk
set_location_assignment PIN_AM10 -to mgmt_clk
set_location_assignment PIN_AL10 -to "mgmt_clk(n)"
#SPI
# set_location_assignment PIN_ -to spi_MISO
# set_location_assignment PIN_ -to spi_MOSI
# set_location_assignment PIN_ -to spi_SCLK
# set_location_assignment PIN_ -to spi_SS_n[0]
set_instance_assignment -name VIRTUAL_PIN ON -to spi_MISO
set_instance_assignment -name VIRTUAL_PIN ON -to spi_MOSI
set_instance_assignment -name VIRTUAL_PIN ON -to spi_SCLK
set_instance_assignment -name VIRTUAL_PIN ON -to spi_SS_n[0]
#sysref
set_instance_assignment -name IO_STANDARD LVDS -to sysref_out
set_instance_assignment -name IO_STANDARD LVDS -to "sysref_out(n)"
set_location_assignment PIN_AW9 -to sysref_out -comment IOBANK_3A
set_location_assignment PIN_AW10 -to "sysref_out(n)" -comment IOBANK_3A
#syncn
set_instance_assignment -name IO_STANDARD LVDS -to sync_n_out
set_instance_assignment -name IO_STANDARD LVDS -to "sync_n_out(n)"
set_location_assignment PIN_AG15 -to sync_n_out -comment IOBANK_3A
set_location_assignment PIN_AF15 -to "sync_n_out(n)" -comment IOBANK_3A
#set_location_assignment PIN_ -to sma_clkout
set_location_assignment PIN_R5 -to global_rst_n
#set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
# Virtual pins
set_instance_assignment -name VIRTUAL_PIN ON -to rx_link_error[*]
set_instance_assignment -name VIRTUAL_PIN ON -to tx_link_error[*]
# Virtual pins
set_instance_assignment -name VIRTUAL_PIN ON -to avst_usr_dout[*]
set_instance_assignment -name VIRTUAL_PIN ON -to avst_usr_dout_valid[*]
set_instance_assignment -name VIRTUAL_PIN ON -to avst_usr_dout_ready[*]
set_instance_assignment -name VIRTUAL_PIN ON -to avst_patchk_data_error
set_instance_assignment -name VIRTUAL_PIN ON -to avst_usr_din[*]
set_instance_assignment -name VIRTUAL_PIN ON -to avst_usr_din_valid[*]
set_instance_assignment -name VIRTUAL_PIN ON -to avst_usr_din_ready[*]
set_instance_assignment -name VIRTUAL_PIN ON -to spi_SS_n[1]
set_instance_assignment -name VIRTUAL_PIN ON -to spi_SS_n[2]
#VID assignments
set_global_assignment -name USE_PWRMGT_SCL SDM_IO14
set_global_assignment -name USE_PWRMGT_SDA SDM_IO11
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTM4677
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 4F
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "AUTO DISCOVERY"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
set_global_assignment -name LAST_QUARTUS_VERSION "23.4.0 Pro Edition"
set_global_assignment -name BOARD "Intel Arria 10 SX SoC Development Kits DK-SOC-10AS066S-D"
set_global_assignment -name SYSTEMVERILOG_FILE altera_jesd204_ed_RX_TX.sv
set_global_assignment -name QSYS_FILE altjesd_ed_qsys_RX_TX.qsys
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_core_pll.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_frame_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_link_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_mgmt_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_JTAG_AVMM_Bridge.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_JTAG_reset.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_pio_control.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_pio_status.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_jtag_rst_bridge.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_reset_controller_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_spi_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_xcvr_atx_pll_0.ip
set_global_assignment -name QSYS_FILE altjesd_ss_RX_TX.qsys
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_frame_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_altjesd_RX_TX.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_link_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_mgmt_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_reset_seq.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_mm_bridge.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_rx_frame_reset_n_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_rx_link_reset_n_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_tx_frame_reset_n_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_tx_link_reset_n_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_xcvr_reset_control_0.ip
set_global_assignment -name IP_FILE ip/altjesd_ss_RX_TX/altjesd_ss_RX_TX_device_clk.ip
set_global_assignment -name IP_FILE ip/altjesd_ed_qsys_RX_TX/altjesd_ed_qsys_RX_TX_device_clk.ip
set_global_assignment -name VERILOG_FILE altera_std_synchronizer_nocut.v
set_global_assignment -name IP_FILE altera_jesd204_se_outbuf_1bit.ip
set_global_assignment -name SYSTEMVERILOG_FILE pattern/ramp_checker.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/prbs_checker.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/pattern_checker_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/alternate_checker.sv
set_global_assignment -name SYSTEMVERILOG_FILE transport_layer/altera_jesd204_deassembler_nprime12.sv
set_global_assignment -name SYSTEMVERILOG_FILE transport_layer/altera_jesd204_deassembler.sv
set_global_assignment -name SYSTEMVERILOG_FILE transport_layer/altera_jesd204_transport_rx_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/ramp_generator.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/prbs_generator.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/pattern_generator_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE pattern/alternate_generator.sv
set_global_assignment -name SYSTEMVERILOG_FILE transport_layer/altera_jesd204_assembler_nprime12.sv
set_global_assignment -name SYSTEMVERILOG_FILE transport_layer/altera_jesd204_assembler.sv
set_global_assignment -name SYSTEMVERILOG_FILE transport_layer/altera_jesd204_transport_tx_top.sv
set_global_assignment -name VERILOG_FILE switch_debouncer.v
set_global_assignment -name VERILOG_FILE spi_mosi_oe.v
set_global_assignment -name VERILOG_FILE spi_3wire.v
set_global_assignment -name VERILOG_FILE ed_perst.v
set_global_assignment -name SDC_FILE altera_jesd204_ed_RX_TX.sdc
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