JESD204B Link Up issues in Arria10 FPGA

[VenkateshK]

Hi,

we ae testing Arria10 with ad9082 , We made design with 2 lanes which is working absolutely fine, same design I have upgraded to 4 lanes by making required changes. In this design ,I am facing an issue that one of the lanes is not recovering BCBC characters properly ,it results that sync is high for some time then it is becoming low .Remaining 3 lanes I am getting Proper BCBC characters.

My design contains HPS and Converters configuration is done through HPS using SPI IP

Any suggestions to solve this issue!

Thanks in advance!

[Harshx]

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case and get back to you soon once I have any finding.

Meanwhile can I check with you on:

1. Device ID you are using?
2. Quartus version?
3. BCBC characters?

You can refer this: 1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware...

I suggest you check your lanes (hardware connection) as well.

Thanks for your patience.

Best regards,

Harsh M

[Harshx]

Hi,

We have not heard back from you for days.

I will proceed to set this case to close-pending since solution has been provided.

Thanks for using Intel Support.

Regards,

Harsh M

[VenkateshK]

Hi Please find my response below:

1. Device ID you are using? - AD9082 and Arria 10 SX
2. Quartus version? - 22.3
3. BCBC characters? - K28.5 characters in JESD