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Hi all,
I am a beginner of Altera's device. Today, When I use the JTAG mode of Quartus’ programmer to configure the device EP3C5E144, the programmer always says “Unable to scan device chain. Can’t scan JTAG chain.” When the programmer tried to scan the chain, I test the TDI, TDO, and TCK. There is data wave on TCK and TDI, but the TDO never changed and always hold about 2.2V. All the power, 1.2V, 2.5V, 3.3V, is OK. I used 2.5V to power the JTAG connector, and added a 1k resistor between 2.5V and 3.3V (pin 6). Besides, NCE holds 0V. Though I have pulled up the signals, Config_done and nstatus, they all keep 0.033V. I also use a flash to configure the FPGA in AS mode. The programmer can download code to flash successfully, however the FPGA shows no action no matter I re-power up the system or not, and there is no clock on DCLK. The Usb blaster should be right, because I can configure some other boards. Could anybody give me some suggestion?Link Copied
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How about TMS? Any activity there?
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Yes, the normally value of TMS is 3.3V and during the scan period, there will be some low level signals.
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Well if your usb blaster is ok, all the connections are right and there's activity on all JTAG input signals, probably your device is broken.
Any chance you could post the schematics of your design? -- Ton- Mark as New
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Thank you Ton.
I have soldered two boards. And they all show the same phenomenon. I don't think the FPGA is broken also because the config_done and Nstatus are nearly 0. However, I don't know where is the problem. I have attached the schematic and I hope some people could tell me why.- Mark as New
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Did you connect the FPGA's exposed pad to ground? Your schematic doesn't seem to mention it.
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--- Quote Start --- Thank you Ton. I have attached the schematic and I hope some people could tell me why. --- Quote End --- The schematic looks ok to me. How about Daixiwen's remark? The exposed pad should definitely be connected to GND. Succes, Ton
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Hi Ton and Daixiwen,
I treated this expose pad for heat emission and placed a big pad under it. However, I don't connect the expose pad to GND. Is this very important? Anyway, I will have a try. Would you please help me to think about whether there is other possible issue?Thank you very much.- Mark as New
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Yes, it is important. See page 1-4, note 7 of the CIII Handbook.
It's just a small note in a big handbook, but important. Success, Ton- Mark as New
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You should try that first Bad exposed pad connections are well known to cause problems with JTAG communications.
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When I connect the pad to GND, I can configure the FPGA in JTAG. In the programmer, I select the JTAG mode and click auto detect, the software can find a device EP3C10, not EP3C5E144. However, if I just add the “.sof” file directly, then the code can be download successfully and FPGA perform a right action.
Thank you, Ton and Daixiwen.- Mark as New
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Dear all:
I have the same problem with ytggsitp when configuring the device EP3SL340H1152. the VVCCIO of bank 1A is 2.5V.When the programmer tried to scan the chain, I test the TDI, TDO,TMS and TCK. There is data wave on TCK ,TMS and TDI, but the TDO never change and always hold about 0 V(Why?I think the output of TDO should be at 2.5V at the begining,am I right?? ). All the power is OK. Thank you very much!!!:)- Mark as New
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--- Quote Start --- Well if your usb blaster is ok, all the connections are right and there's activity on all JTAG input signals, probably your device is broken. Any chance you could post the schematics of your design? -- Ton --- Quote End --- Dear Ton: I have the same problem with ytggsitp when configuring the device EP3SL340H1152. the VVCCIO of bank 1A is 2.5V.When the programmer tried to scan the chain, I test the TDI, TDO,TMS and TCK. There is data wave on TCK ,TMS and TDI, but the TDO never change and always hold about 0 V(Why?I think the output of TDO should be at 2.5V at the begining,am I right?? ). All the power is OK. Thank you very much!!!
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Difficult to say, with this little information. Is there a chance you could post your schematic?
TDO is high-Z in the beginning. So you should see a high on this pin, if it has a pull-up resistor. -- Ton- Mark as New
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The Vccpd = Vccio1A = 2.5V
The program connector is powered by V_3.3 These should be the same (either V_3.3 or 2.5V). nSTATUS and nCONFIG and CONFIG_DONE should be pulled-up to Vccpgm, which is 3.3Vcc, not V_3.3. Maybe these are supposed to be the same, but in your schematic the labels differ. Pull-up JTAG to Vccpd. Pull-up other programming pins to Vccpgm. Good luck, Ton- Mark as New
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Now I get Vccpgm = Vccpd = Vccio1A = 2.5V and the program connector powered by V_3.3.
nSTATUS 、nCONFIG and CONFIG_DONE are all pulled-up to Vccpgm which is 2.5V. However,the question still exists. when operating autodetector, both device chain and JTAG chain couldn't be scaned. It's puzzled to me that TDO still holds low level and is never changed. However, it works well in the PS mode configuration. In addition, it is nornal for the output of Bank 1A that TDI, TDO TCK and TMS belongs to. Many thanks!Best wishes to you!- Mark as New
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--- Quote Start --- The Vccpd = Vccio1A = 2.5V The program connector is powered by V_3.3 These should be the same (either V_3.3 or 2.5V). nSTATUS and nCONFIG and CONFIG_DONE should be pulled-up to Vccpgm, which is 3.3Vcc, not V_3.3. Maybe these are supposed to be the same, but in your schematic the labels differ. Pull-up JTAG to Vccpd. Pull-up other programming pins to Vccpgm. Good luck, Ton --- Quote End --- Now I get Vccpgm = Vccpd = Vccio1A = 2.5V and the program connector powered by 2.5V. nSTATUS 、nCONFIG and CONFIG_DONE are all pulled-up to Vccpgm which is 2.5V. However,the question still exists. when operating autodetector, both device chain and JTAG chain couldn't be scaned. It's puzzled to me that TDO still holds low level and is never changed. However, it works well in the PS mode configuration. In addition, it is nornal for the output of Bank 1A that TDI, TDO TCK and TMS belongs to. Many thanks!Best wishes to you!

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