JTAG programming of MAX V and Cyclone IV

[Altera_Forum]

Hi 

 I want to put both a MAX V and Cyclone IV on the same JTAG chain so they can both be programmed via a USB blaster. VCCIO for both devices is +3.3V. From the manuals the MAX V needs a +3.3V supply to the USB blaster but for the Cyclone IV the supply to the USB blaster should be +2.5V. Is it possible to make this work?  Thanks Ian

[Altera_Forum]

I would operate the JTAG interface completely at 3.3V and provide clamp deiodes as overvoltage protection.

[Altera_Forum]

hello  

 i am also using cyclone IV device and i am trying to configure my FPGA in jtag mode.  i am using FT2232HL for USB to JTAG protocol conversion.  but when i try to detect my device in UrJTAG console i an receiving a Warning saying  TDO seems to be stuck a 0.  i have checked all my connections 10 times, they all are as per the cyclone IV design guide and Pin connection guidelines provided by altera.  to be more specific here is the link from where i made the connection for the jtag mode of configurations.  "forum banned the link"  i have also give the path for the bsdl file in UrJTAG shell.   i am not able to figure out what is the problem and why is my FPGA not getting detected.  please let me know if you have any idea as yours design seems to work with cpld and fpga.  Regards  Saurabh Agrawal

[Altera_Forum]

Altera devices use the four JTAG pins for JTAG programming or configuration. They should be connected as below: 

 

1. TCK (Test Clock) - From download cable in parallel to every device in the JTAG chain. Weakly pulled-down to GND. Check the Configuration Handbook or specific device Handbook for resistor values. 
2. TMS (Test Mode Select) - From download cable in parallel to every device in the JTAG chain. Weakly pulled-up to VCCIO. Check the Configuration Handbook or specific device Handbook for resistor values. 
3. TDO (Test Data Out) - The TDO pin of a device is connected to the TDI pin of the subsequent device in the JTAG chain. For the last device in the JTAG chain, the TDO pin is connected to the TDO pin of the download cable. 
4. TDI (Test Data In) - TDI pin of a device is connected to the TDO pin of the preceding device in the JTAG chain. For the first device in the JTAG chain, the TDI pin is connected to the TDI pin of the download cable. 

  Even though other programming or configuration pins (for FPGA) are not used in JTAG mode, they must be properly connected and cannot be left floating.   

1. nTRST - Driven high during JTAG configuration. 
2. nCE - Connect to GND or driven low during JTAG configuration. 
3. MSEL pins - Connect to ground. 
4. nCONFIG - Driven high or pulled to VCC through a pull-up resistor. 
5. DCLK - Either pull-up or pull-down through resistor. 
6. DATA pin(s) - Either pull-up or pull-down through resistor. 
7. nSTATUS - Pull to VCC through a pull-up resistor. When the device is powered-up, this pin will be released to high. 
8. CONF_DONE - Pull to VCC through a pull-up resistor. Should be pulled-up individually for the devices in a chain. When the device is successfully configured, this pin will be released to high. 
9. INIT_DONE - When used, pull-up to VCC. 

[Altera_Forum]

Can you check the JTAG signals with a scope and verify that they are all toggling?