Key features on Stratix II

[Altera_Forum]

1. Do any of the Altera FPGAs have integrated hardwired Tri-Mode Ethernet MACs, as does Xilinx? 

 2. Do any of the Altera FPGAs have integrated hardwired PCI Express™ Endpoint blocks, as does Xilinx?   3. Do any of the Altera FPGAs have integrated hardwired serial processor, as does Xilinx with PowerPC?

[Altera_Forum]

Er, um, well... maybe, I guess not. : ) 

 The first question I would like to as is why? I only ask that because my worry is that they look compelling on paper, but often aren't that way in real life. Are you choosing an architecture and feel you'll need these three features? Is this for a particular design, or are you choosing an architecture for multiple designs, or is this maybe research for inside your company?   Note that I typed up a reply on all three, but deleted them, realizing this is one of those issues people could argue about for days without ever reaching a conclusion. So rather than just throwing out some blanket statements, I was wondering if you could clarify what you're looking for and trying to do, and maybe your thoughts on these three items(if you think you need them as Hard IP, prefer them as soft IP, etc.). There should be some experts that follow this board who can do a much better job pointing out the pros and cons on each topic(as it's different for each one), and hopefully provide you guidance with whatever it is you're trying to accomplish. As the question is phrased now, it feels kind of like a minefield(not that this was your intent, but it's very open ended and makes it too easy to not answer what you're really looking for.) Thanks.

[Altera_Forum]

Ignoring the title of the thread; 

 1. No.  2. No.  3. Yes.  On item 2, I recall going to a Xilinx seminar hosted by Insight Electronics I believe, where they had a factory marketing person presenting. He was asked if Xiloinx would ever be placing the PCI core in a hard block in the FPGA, like ACTEL was offering at the time. His reply was a solid NO, as they had felt that having a hard macro frozen at a particular revision of the PCI spec. was a losing proposition and were fully committed to keeping the IP in FPGA fabrix to allow for continued flexibility for the user.  On items 3, I believe that Altera offered the ARM processor in the Excalibar line at one time. Here again, while it seems nice to offer a higher performance processor directly in the FPGA fabric, practical limitations in terms of wrapping the rest of the infrastructure about the hard IP can result in various challenges that effect overall system performance.  I hope this answers your questions as asked above.  I hope this also fosters additional dialogue from others for their viewpoints.

[Altera_Forum]

Ignoring the title of the thread; 

 1. No.  2. No.  3. Yes.  On item 2, I recall going to a Xilinx seminar hosted by Insight Electronics I believe, where they had a factory marketing person presenting. He was asked if Xilinx would ever be placing the PCI core in a hard block in the FPGA, like ACTEL was offering at the time. His reply was a solid NO, as they had felt that having a hard macro frozen at a particular revision of the PCI spec. was a losing proposition and were fully committed to keeping the IP in FPGA fabric to allow for continued flexibility for the user.  On items 3, I believe that Altera offered the ARM processor in the Excalibar line at one time. Here again, while it seems nice to offer a higher performance processor directly in the FPGA fabric, practical limitations in terms of wrapping the rest of the infrastructure about the hard IP can result in various challenges that effect overall system performance.  I hope this answers your questions as asked above.  I hope this also fosters additional dialogue from others for their viewpoints.

[Altera_Forum]

I think if you compare Altera's Nios processor against Xilinx's Micro Blaze or comparable soft processors you'll see that they really can't compare with Nios.  

 I also suggest looking at the Altera IP partners for alternalte implementations to achieve your design goals.