LIFO and Cyclone Altsyncram (addressing problem)

Altera_Forum · ‎11-03-2009

Hi, I must do a LIFO (Last IN First Out) whith altera Cyclone altsyncram megafuncion. And in this place I have a problem.. I don't now how create a write and read procedure.. whith different kinds of types, address.

This is my code

PORT
    (   wrreq : IN STD_LOGIC;
        rdreq : IN STD_LOGIC;
        rst : IN STD_LOGIC;
        data1 : IN STD_LOGIC_VECTOR(2 downto 0);
        clck : IN STD_LOGIC;
        data : OUT STD_LOGIC_VECTOR(2 downto 0);
        wraddress : OUT STD_LOGIC_VECTOR(2 downto 0);
        rdaddress : INOUT STD_LOGIC_VECTOR(2 downto 0)
    );
    -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
    
Type MEMOR is array(0 to 7) of STD_LOGIC_VECTOR(2 downto 0);
signal TAB : MEMOR := ("000", "001", "010", "011", "100", "101", "110", "111");
signal WRRAD, RDRAD : Natural range 0 to 7;    
signal WRBuffer, RDBuffer : Std_Logic_Vector(2 downto 0);
    
END;
--  Architecture Body
ARCHITECTURE architecture OF  IS
BEGIN
Write : process is
BEGIN
wait until rising_edge(clck);
if rst = '1' then
WRRAD <= 0;
WRBuffer <= (others => '0');
RDBuffer <= (others => '0');
data <= (others => '0');
end if;
if wrreq = '1' then 
WRBuffer <= TAB(WRRAD);
WRRAD <= (WRRAD + 1) mod 7;
data <= Std_Logic_Vector (data1);
end if;
if rdreq ='1' then
RDBuffer <= TAB(RDRAD - 1);
RDRAD <= (RDRAD - 1) mod 7;
end if;
end process;
wraddress(i) <= (WRBuffer) when wrreq = '1'
else (others => 'Z'); 
rdaddress(i) <= (RDBuffer) when rdreq = '1'
else (others => 'Z');
END _architecture;

Writing suppose to be a wraddress (WRRAD) <= data hmm.. I dont have any idea how to make it..

THX for any help