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LPDDR2 Interfacing to CycloneV

Altera_Forum
Honored Contributor II
‎03-23-2016 10:00 AM
1,081 Views

Hi, 

 

In general, from Board design perspective,  

What is the process (with quartus SW) for planing LPDDR2 interface on CycloneV? 

For example how to determine which BANK/IO to use 

 

 

Thanks
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Altera_Forum
Honored Contributor II
‎03-24-2016 09:52 AM
391 Views

I strongly recommend you put a simple FPGA design together (it need only be simple), instantiating the LPDDR interface, run it through Quartus and let Quartus choose a pinout. 

 

Decide if you can work with that. If so, great. If not constrain it to use your preferred bank(s) and run that through Quartus again. 

 

Remember, you will always be able to shuffle DQ pins within a byte lane. 

 

Cheers, 

Alex
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