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LUT with Size 500 000

Altera_Forum
Honored Contributor II
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hello , 

 

could someone tell me how i can realize a LUT with size 500000 for FPGA in verilog? 

 

thanks
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Altera_Forum
Honored Contributor II
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A LUT with 500,000 entries? And how many bits is each entry? 

 

I suggest you declare an array and then use the inital block to set the values. 

 

reg [7:0] lut_rom [0:499_999]; 

integer i; 

initial begin 

for(i = 0; i < 500_000; i = i+1) begin 

lut_rom[i] = .... 

end 

end 

 

Reads should be performed in such a way that Quartus can infer a synchronous ROM from this. Otherwise, it will probably not fit and/or be very slow.
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