LVDS Receiver PLL

[Altera_Forum]

I am using using a Stratix II with Quartus 7.1 SP1. 

 When using an LVDS receiver the fitter automatically assigns the input clock as LVDS as well. How would I clock the LVDS receiver using single ended LVTTL?

[Altera_Forum]

Hello, 

 following the Stratix II manual, single-ended IO-standards as LVCMOS should be able to clock Fast PLLs. The restrictions applied by the fitter seems to be beyond device specification and thus a misbehaviour to be corrected. I was able to connect a global clock driving other parts of the design to Fast PLL input - with the aid of a clock control block instance.  Apart from what is allowed in the manual, it may be meaningful to use a differential standard anyway. Probably a pseudo LVDS signal made by resistive dividing of a LVCMOS clock is less sensitive to ground bounce than a ground referenced clock. At best use a real LVDS driver, e. g. a single gate SN65LVDS1.  Regards,  Frank

[Altera_Forum]

Hello once again, 

 scanning the documentation for the keyword "same i/o standard", I finally could find a sentence mentioning the said restriction under PLL Clock Feedback Modes. For Zero Delay and External Feedback Mode a restriction applies:  --- Quote Start ---  Altera requires that you use the same I/O standard on the input clock, and output clocks.  --- Quote End ---  The point is, if I understand right, that using the same I/O standard is necessary to achieve a specified PLL timing relationship. In my example, however, he PLL is using normal feedback mode. For this mode, no restriction regarding I/O standards is written in the manual. Using DPA to achieve source synchronous LVDS receiver timing, this seems reasonable.  Additionally, the restrictions, as far as they really exist, should be listed in the PLL Pin overview and in the Clocking and I/O-Standards chapters.  Regards,  Frank

[Altera_Forum]

Frank, 

 What version of Quartus are you using? I've tried this on 7.1SP1 and 7.2SP1 and get the same results. I understand that using an LVDS clock is ideal. However, my PCB is already complete and all I have are single ended clocks.   If you know of a way to get clock the LVDS receiver then please take me through it step by step. Currently, when creating a PLL for the LVDS receiver in the MegaWizard Plugin Manager there is a checkbox for "set-up PLL in LVDS mode". When I check this the PLL is automatically set to Fast PLL in Normal Mode. The other options are ghosted. As you stated in your previous post the PLL should be in "normal feedback mode". I believe that I have achieved this and yet the fitter continues to cry about the "same I/O standard" and automatically assigns the clock to LVDS.  Please advise.  Thanks, Shane

[Altera_Forum]

Hello Shane, 

 to be true, I'm a bit confused with Quartus behaviour in this point. What I reported in my posting was something, I just tried to understand if clocking LVDS input Fast PLL with single-ended I/O standard would be possible or not. From the manual, it's clear that the clock signal should be originated either from a dedicated clock input or another PLL. With an otherwise unconnected clock input, this resulted in transfoming the clock input to LVDS, as you reported. This also happened in one case with a clock driving other parts of the design. Then I inserted a clock control block instance manually and the existing clock remains untouched. Quartus issued a warning about the PLL not clocked by an dedicated input but was willing to fit the design.  But this was only an arbitrary test case, I'm not sure about all factors that caused the said result. Now I was aware, that the design I'm just working on, has basically a similar clocking scheme. I have a "main" clock, driven from a single ended input, using a PLL etc. A LVDS receiver part had been planned to use an external LVDS input clock. Cause this external clock is actually a backfeeded derived main clock, I connected the main clock input internally to LVDS receiver block instead, and it works. Probably I could also use a PLL generated clock, but the consideration was not cascading PLLs if unnecessary. The LVDS receiver is standard Megawizard generated with "internal" PLL, just for convenience.  Actually, this is an Arria rather than an Stratix II design, but clock networks are allmost identical between both devices. It seems to me, that there is no difference using V7.1 or V7.2, I got identical behaviour in this respect with both Quartus II versions.  As a conclusion: Quartus, at least, seems to be able to use an single-ended clock input to a clock network already existing in the design as LVDS receiver clock without transforming the I/O standard unasked. Possibly, additional conditions must be met to achieve this.  Regards,  Frank

[Altera_Forum]

I have heard of this problem before and I believe there is a software patch available to allow a different IO standard for the LVDS PLL reference clock. I believe I've read somewhere the LVDS restricition is to achieve the best possible jitter tolerance to maximize timing margin at the highest rates. 

 I would recommend filing a service request with Altera's mySupport for access to the software patch.  Regards,  Chris  Edit: I see Frank found a work around using the clkctrl... try that first ;)