Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

LVDS input on MAX V CPLDS?

Altera_Forum
Honored Contributor II
‎10-04-2013 03:28 PM
1,790 Views

The guide for the MAX V CPLDs only states that it supports LVDS output. It does not explicitly mention supporting LVDS input. 

 

My assumption is that LVDS input is not supported, however, it would be nice to be sure. 

 

Can anyone enlighten me? 

 

Thanks
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎10-04-2013 05:56 PM
939 Views

Essentially, you're right. However, to expand slightly... 

 

Max V CPLDs support an 'Emulated LVDS Output Standard'. By driving an external resistor network, along with a further resistor at the input of the remote LVDS receiver, they can support LVDS links. 

 

They do not support LVDS directly on their input pins in the same way various FPGA families do. If you want to drive LVDS signals into a MAX V CPLD you will need an external LVDS receiver. 

 

Refer to application note 636 for more information: 

http://www.altera.co.uk/literature/an/an636.pdf (http://www.altera.co.uk/literature/an/an636.pdf) 

 

Regards, 

Alex
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.