LVDS interconnect

[Altera_Forum]

Hi all 

I designed a board, There are two FPGAs, One is ep1agx50 , anothers is ep2s130. About 6 months ago, I can transmit data form ep2s130 to ep1agx50 through LVDS, But now, The ep1agx50 can't receive any correct data. I checked the schematic, and found that ep2s130 PLL－ENA pin left float, Is it reason?  Thanks forward.

[Altera_Forum]

PS: Clock frequency : 100Mhz, deser factor : 1, bus width : 8

[Altera_Forum]

The Stratix II device handbook clarifies, that PLL_ENA must be connected to GND, if not used in your design.