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Hi,
I want to implement a LVDS interface between two boards, one has Cyclone 10lp and 2nd board has Cyclone V GT.
Cyclone10 lp is required to be a Transmitter and Cyclone V will act as Master Recevier providing the interface clock / LVDS clock to cyclone 10 lp. The requirement of data transfer speed is max 200Mbps.
I need help to understand the architecture for Master Recevier and Transmitter using LVDS and how it should be implemented.
1. What components should be on the Master Recevier
2. What comopnents should be on the Transmitter side
3. How the LVDS interface will be synchronised
Any feedback will be helpful.
Thank you
With Regards
Mohsin
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Hi,
the preferred clocking scheme for fast serial interfaces is source synchronous with clock recovery from data stream ( CDR). Unfortunately Cyclone series doesn't offer generic CDR, except for Cyclone 10 GX. It's basically possible to implement soft CDR in FPGA fabric, but there are no Intel reference designs so far. Next best option is to send TX clock along with the data. Sending a frame clock with bit clock regeneration on the receiver side also solves the problem of frame synchronization.
You are apparently planning to distribute a master clock from the receiver, but it's still useful to return a TX clock for easier delay compensation (presumed you don't have a CDR option).
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Thank you, Frank, for the useful input.
Hello Mohsin,
May I know if you need any more information on this?
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I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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