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Altera_Forum
Honored Contributor I
825 Views

LVDS signals transmitting and receiving Using I/O buffers

Hello,  

 

I have gone through lot of tutorials and am totally confused :confused:. I am new to Altera, so i don`t how to proceed with the design. Please anyone explain me how to start-up this design.  

 

Task: 

 

I need to give counter signals as LVDS signals. The LVDS signals should be transmitted to Cyclone V board. Please guide me.  

 

Whether i can go for Block design using quartus IP core or how. If using Block design means, how to program my board. Need workflow of this process.
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Altera_Forum
Honored Contributor I
69 Views

The preferred way to implement LVDS signals (or other differential IO standards) is to use simple single ended ports in the top design (either HDL or schematic) and to assign LVDS I/O standard in the pin planner. The port has to be assigned to the positive LVDS pin, the negative pin is chosen automatically by the fitter. 

 

All IP cores can be used in schematic design, symbols are generated on request.
Altera_Forum
Honored Contributor I
69 Views

 

--- Quote Start ---  

The preferred way to implement LVDS signals (or other differential IO standards) is to use simple single ended ports in the top design (either HDL or schematic) and to assign LVDS I/O standard in the pin planner. The port has to be assigned to the positive LVDS pin, the negative pin is chosen automatically by the fitter. 

 

All IP cores can be used in schematic design, symbols are generated on request. 

--- Quote End ---  

 

 

Thanks for your response.  

 

Two more doubts 

1. Shall i integrate counter IP and IBUF IP together as a single block design file, and import into QSYS. Please explain the process 

 

2. Shall i call this IP in Qsys, and implement the bit file using NIOS because i need to verify the LVDS output.
Altera_Forum
Honored Contributor I
69 Views

How to connect 4-bit counter to outbuff_diff of 4 bit ?

Altera_Forum
Honored Contributor I
69 Views

Nothing specific to differential signaling, I believe. You cant do as with other multi-bit signals in schematic design. 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14986  

 

As previously mentioned, you don't need DIFF_BUFFER to connect LVDS.
Altera_Forum
Honored Contributor I
69 Views

Hi,  

 

Actual requirement is take 128 pairs of LVDS signals from my Board. So how can i do this [multi-bit signals]. Please explain me the design process. It will be grateful to me.  

 

How can i do this ? 

 

Thanks.
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