Learn FPGA design

[Altera_Forum]

Hey ppl, 

 I want to learn FPGA design, I even bought development board DE2. What I need now is a good source of information. I understood that the most famous HDL language is Verilog. I know it a little bit.  What I need is to learn how is to describe the system functionality in the right way, what is the right way to write test benches, and so on.  Do you know where can I get this information in the best way described?  Thanks ahead

[Altera_Forum]

Yes, there are a lot of info there.  

but what I need is not a Verilog as syntax but how to describe the system I want to do. I look something like circuit and its description in Verilog. Does someone know where can I get this examples?

[Altera_Forum]

Hi, 

I know one book "FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version", maybe it can help you

[Altera_Forum]

The same book you have for VHDL, "FPGA Prototyping By VHDL Examples: Xilinx Spartan-3 Version "

[Altera_Forum]

Good luck!

[Altera_Forum]

Thank you very much

[Altera_Forum]

Back in the day I learned VHDL using the tutorials built into the Aldec tools. They go though various levels in an automated tutorial type of flow. That was a long time ago but I hear they still have it and if it was good back then it must be even better by now. 

 One really important thing in my opinion is to find HDL examples that use a clean style (just like in software). I learned verilog the hard way and picked up all kinds of bad styles along the way when starting out. I use a really ridged style now where I separate everything combinational from the register assignments which avoids all the gotchas that verilog offers. This method is very handy (I think) because any time I want to change the control behavior it's all located in one spot and I don't need to touch anything in the register portion of the code. It also prevents doing foolish things like creating latches by accident since that's a big no-no when it comes to FPGA design usually. Here is an example of what I'm talking about: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html Any time I update that design I can literally look at a single screen of combinational assignments to fix bugs or add enhancements without even looking at the mess of registers and submodule instantiations that reside above the combinational code. For those of you in school you might hear the term "RTL" as in "register transfer level" taught ..... that's what I just described and when it comes to large scale design I consider it the *only* style worth using.

[Altera_Forum]

3Q----------

[Altera_Forum]

--- Quote Start ---  Hey ppl,  I want to learn FPGA design, I even bought development board DE2. What I need now is a good source of information. I understood that the most famous HDL language is Verilog. I know it a little bit.  What I need is to learn how is to describe the system functionality in the right way, what is the right way to write test benches, and so on.  Do you know where can I get this information in the best way described?  Thanks ahead  --- Quote End ---   BadOmen already gave excellent advice. Any design has data flow and control logic and the control logic is the key to the functionality. The System has inputs, data manipulation, and outputs. So if you put together what is necessary to explain your new system to someone else, you will have a good start. HDL is a description language in text format that is used to define the hardware to the EDA programs that convert to physical circuitry. In the process Register Transfer Level data are generated and simulation can then produce waveforms for the test bench.  The test bench applies inputs and generates simulated outputs. To verify a design exhaustively the test bench would have to have every combination of inputs for the system ... it may practical to partition the system so the partitions can be verified independently with overall verification at a higher level.   Recently there was a thread started by BuGless about HDL vs Schematic design entry and it seems that starting with a block/flow diagram for the big picture then using HDL for the detailed design may work pretty well. It was a long discussion, but food for thought.

[Altera_Forum]

try this site http://www.asic-world.com/verilog/veritut.html

[Altera_Forum]

hi, simKnutt, 

This site is also quite good for you http://members.optushome.com.au/jekent/fpga.htm