Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20780 Discussions

Leaving target processor paused

Altera_Forum
Honored Contributor II
1,300 Views

When I try to run simple hello_led project using CII_Starter_NIOS.sof and corresponding .ptf file I get the following error and nothing happens next: 

 

Verifying 00400000 ( 0%) 

Verify failed between address 0x400000 and 0x4000D3 

Leaving target processor paused 

 

What is the cause of this error? 

 

Thanks
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
477 Views

Hi, 

i've encounterred this problem , maybe there's something wrong with your memory module . if you use a sdram , check the clock phase and settings of the sdram controller. 

good luck to you
0 Kudos
Altera_Forum
Honored Contributor II
477 Views

This typically occurs when your memory interface is not working properly (usually because you've not connected it properly or it's not meeting timing constraints). 

 

Jake
0 Kudos
Altera_Forum
Honored Contributor II
477 Views

So what exactly I need to do? Where do I need to connect it and what time constraint should be met? 

I have QuartusII web edition so will I be able to change the settings? 

 

 

Thanks for the HELP! 

Best Regards, 

Nishant
0 Kudos
Altera_Forum
Honored Contributor II
477 Views

Please try a search on the forum for other posts regarding your same problem as this question has been answered many times before. 

 

Jake
0 Kudos
Reply