Logic lock

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How to make many logic locks that are exactly the same as one logic lock?

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--- Quote Start ---  How to make many logic locks that are exactly the same as one logic lock?  --- Quote End ---    Hi,  do want to duplicate a LogicLock region ????

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yes, and how to connect the newly generated ports after duplication?

[Altera_Forum]

Should I export a logic lock containging an entity, then import 10 such logic locks, and then how to connect the ports of these 10 entities to other ports?

[Altera_Forum]

Hi, 

 you got it half and half...   Yes you export/import from lower level to higher level but you connect your ports as usual through your project build-up. The compiler will then know you want the locked module to be there.   This is similar to incremental compilation. I personally don't recommend either unless it is very necessary as it has its limitations e.g. yo can't use signaltap (at least as far as I know).   kaz

[Altera_Forum]

--- Quote Start ---  Hi,   you got it half and half...   Yes you export/import from lower level to higher level but you connect your ports as usual through your project build-up. The compiler will then know you want the locked module to be there.   This is similar to incremental compilation. I personally don't recommend either unless it is very necessary as it has its limitations e.g. yo can't use signaltap (at least as far as I know).   kaz  --- Quote End ---    Hi Kaz,  I never heard that I can't use signaltap when using incremental compilation. My experience is that it works fine. In order to get the most benefit of incremental Compilation and signaltap you should choose only post-fitted nodes. in this case only the connection to signaltap are new routed. But you can also choose pre-synthesis nodes, but the P&R will take longer, you influence the sythesis and maybe your timing.

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--- Quote Start ---  Should I export a logic lock containging an entity, then import 10 such logic locks, and then how to connect the ports of these 10 entities to other ports?  --- Quote End ---    Hi sylvest,  what do wanted to achieve ? Do you have a module, 10 times used in your design. Do you have a lower level project for the module alone and you would like to import this into a top-level project ?

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What does "Back annotate the LogicLock Region" mean? 

 How to duplicate a logic lock region into many logic lock regions with the same logic, logic position and routing in the logic lock region?

[Altera_Forum]

--- Quote Start ---  What does "Back annotate the LogicLock Region" mean?   How to duplicate a logic lock region into many logic lock regions with the same logic, logic position and routing in the logic lock region?  --- Quote End ---    Hi Sylvest,  for your tasks I would use design partitions. I have a small project created, which could maybe help you to understand what I'm trying to explain. First I have a subproject created with a simple counter. After succesful P&R I have export the design as design partition. The counter is 4 times used in the toplevel project. These counters instances are also defined as design partitions. For the first run of the toplevel project you need a blackbox for the counter, in order to successful compile the project. Then you have to import the counter design and to define for which design partitons you will use the imported design (in this case for all counters). After import you can run the P&R again, with the setting preserve placement and routing.

[Altera_Forum]

I exported logic lock: 

   load_package flow load_package logiclock load_package backannotate project_new lockmult -overwrite set_global_assignment -name BDF_FILE pipemult.bdf set_global_assignment -name FAMILY CycloneII set_global_assignment -name DEVICE EP2C35F672C6 set_global_assignment -name TOP_LEVEL_ENTITY pipemult# These two assignments cause the Quartus II software# to generate a VQM file for the logic in the LogicLock# region. The VQM file is imported into the top-level# design. set_global_assignment -name  LOGICLOCK_INCREMENTAL_COMPILE_FILE pipemult.vqm set_global_assignment -name  LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT ON create_base_clock -fmax 200MHz -target clk clk_200# assign_virtual_pins { clk }# Prepare LogicLock data structures before# LogicLock-related commands. initialize_logiclock# Create a region named lockmult and assign pipemult# to it.# The region is auto-sized and floating. set_logiclock -region lockmult -auto_size true  -floating true set_logiclock_contents -region lockmult -to pipemult execute_flow -compile# Back annotate the LogicLock Region and export a QSF logiclock_back_annotate -region lockmult -lock logiclock_export -file_name pipemult.qsf -routing uninitialize_logiclock project_close     and then import:   load_package flow load_package logiclock project_new topmult -overwrite set_global_assignment -name BDF_FILE topmult.bdf set_global_assignment -name VQM_FILE pipemult.vqm set_global_assignment -name FAMILY CycloneII set_global_assignment -name DEVICE EP2C35F672C6 create_base_clock -fmax 200MHz -target clk clk_200# The LogicLock region will be used four times# in the top-level design. These assignments# specify that the back-annotated assignments in# the QSF will be applied to the four entities# in the top-level design. set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_1 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_2 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_3 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_4 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_5 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_6 set_instance_assignment -name LL_IMPORT_FILE pipemult.qsf -to pipemult:inst1_7     execute_flow -analysis_and_elaboration initialize_logiclock logiclock_import -do_routing uninitialize_logiclock execute_flow -compile project_close   And then I instantiate the pipemults using VHDL. Why the logic, routing and position of logic in the logic lock region changed?

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how to import one design partition 100 times using tcl script? 

 Thanks!

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--- Quote Start ---  how to import one design partition 100 times using tcl script?   Thanks!  --- Quote End ---     Hi sylvest,  do you think you will go with the partiton based flow ? I have to look for a way with a TCL sccript, because I have use the flow actual only with a few, but larger blocks. I don't know how full your FPGA will be with all the multiplier, but at a high uitiliaztion in would be more difficult to find a fit for your design with the hard requirement to preserve the placement and the routing. BTW that is also a advantange of the partition flow, because you can choose between serveral options ( Placement and Routing, Placement, Netlist ).