Hi,
While compiling one of my designs, I have noticed that there are a lot of ALMs wasted (or rather unusable) in case of Stratix/Arria if my design uses 4:1 mux. Please note that for implementing a 4:1 mux we need to use 6-input LUT and only one 6-input LUT should be sufficient to do this. However because of the ALM architecture which has only 8 inputs one complete ALM is used up for forming a 4:1 mux. So if the design uses 20K 4:1 mux, around 20K ALMs would be used up (might be only slightly less because of the optimization). So if I look in terms of LEs, around 50K LEs are required for this design.
If we are using a Xilinx device with 6-input LUTs (V5 or V6), the same design would require 20K LUTs and hence around 30K LEs.
Note that actual utilization in both the cases may be same, but since there are a lot of unusable LUTs in case of Stratix, the overall utilization increases and hence we may have to use a bigger device in case of Altera.
Is there any workaround for this, or is it a permanent limitation with Altera devices? Can someone please help!!
