Lookup-Table (LUT's)

[Altera_Forum]

Hello 

As a beggner in programming VHDL for the Altera i will be very happy to tell me what is the best way to make a lookup table in the altera, and how much silicon it will cost me ?

[Altera_Forum]

As far as "how much silicon will it cost me", the datasheets should provide an exact number of LUTs that are available in a device. That should be one of your metrics as to what's available in a device. Registers, memory blocks, DSP blocks, IO, PLLs, etc. are other parameters to watch. You don't need to worry about silicon, per se, but how much of a particular device resources are used. Who cares how many LUTs a design takes if the device doesn't have enough IO. 

 As for how to code a lookup table, I strongly suggest not to do this, as you'll get bogged down in the nitty-gritty and never do anything useful. Concentrate on writing at a higher level, like your VHDL. If it doesn't infer what you want, ask what needs to be done in your code to get proper inference. Note that there are some things which can't be inferred, like PLLs or certain DSP block configurations, which the Quartus Megawizard is used for creating. Come back to this board if there's something specific you can't find.  If, after all that, you really need to write a LUT equation, reference the Designing with Low-Level Primitives User Guide: http://www.altera.com/literature/ug/ug_low_level.pdf

[Altera_Forum]

Hey  

Thanks you for your help. but what i need exatly is to build a LUT this way. A. The table will contain the same value for large ranges of counts. I.E. if count is anywhere between 10 and 100 the lookup value is the same. Is there a way to minimize the table so that I only have to list index ranges? In other words it would be nice if the index isn't found, to take the 'nearest' index. B. C) Is there some entirely different way to code the lookup table?

[Altera_Forum]

I think we're confusing each other with terminology. By LUT, I am refering to the Look Up Table before the register within the FPGA, i.e. a 4:1 LUT in Cyclone families, and an adaptive LUT in Stratix II/III. I would not recommend mapping directly to those low-level primitives unless you can't do it any other way. 

 I think what you are building is a ROM(which can alse be called a Look Up Table). In general, I would recommend using the Megawizard Plug-In Manager to build a ROM. You can use initialization files like .mifs, which are sometimes easier when repeating long ranges. The Quartus II handbook also shows how to infer ROMs out of logic, and how to add attributes that point to .mifs.  As for doing pure VHDL, I'm not sure how to specify a range across the ROM. There's probably some slick way, but you could also just wrap it in for-loops and get the same result.

[Altera_Forum]

Thanks u for trying helping me. 

I think i mentioned that i am a beginner and i had make a mistake not telling that i am using the ACEX1K. My next project will be to convert all what I have to Stratix II/III. My question is if it is the same way to build a ROM in both of them Stratix II/III and ACEX1K or u prefer another way to it with the ACEX1K? one more thing is that the output of my LUT is in Hexa is there a way to do this ? or i most convert it to bin ? P.S (my english is not that good I am sorry about the grammer or any other mistakes)

[Altera_Forum]

No problem with the English. If you could though, in future posts, try to put down as much information about your situation as possible. If a ROM was implemented in Acex, there most likely isn't any problem porting it forward to SII/SIII. The only possibility I can think of is I believe Acek RAM had a purely asynchronous read/write mode, where the block rams are synchronous(SIII LUTrams have asynch reads, if you use those). And you can use .hex for these devices too.  

If the design worked in Acex, retarget the compile for Stratix and see what happens. If it already exists, I see no reason to redo everything. But my adivce from before(using the Megawizard to create a ROM, or inferring it in HDL) is still relevant, and can be studied more in the Quartus II Handbook.

[Altera_Forum]

I suspect that there is a way to code this function in VHDL or Verilog with CASE statements. 

The Resulting "HEX" Output would then be assigned for each CASE or Range of Values.  What is the Range of Inputs that you are looing to build the Look Up Table for? You mention the example of from 10 to 100 the result is all the same, are you talking about from 1 to 1000 or from 1 to 65K inputs? Is the Result a single HEX value?  Answer that and I suspect some good programmer will give you an HDL syntax that will work for you. Also state your preferred language.