Low Pass IIR filter using cyclone II FPGA

[Altera_Forum]

Hi everyone, 

I hava a task to implement low pass iir filter on cyclone II FPGA. The parameters of filter are the following: fp=5kHz; pass band frequency fs=8kHz; stop band frequency Fs=44kHz; sampling frequency amax=1db; maximal attenuation in a pass band anim=50db; minimal attenuation in a stop band as a refferent filter I use Chebyshev filter.  After a few calculation I got N=7 for a order of my filter. After that, I got the transffer function H(z) = 8*10^(-6)*(1+z)^7/(z^7-5.515z^6+13.761z^5-20.023z^4+18.29*z^3....  As you see I have to implement multiplication of usigned numbers.  I need advice: which is the best way to implement this recursive formula? I also need to know how many bits-wide operands must be and how to implement multiplication.  Thank you very much for your efforts to help me ! Bojan

[Altera_Forum]

Hi Koce, 

this will depend also on the type of DAC that you are using. If you take care that your digital filter has a unity gain the digital output of the filter will have the same dynamic range of the filter input, which is the ADC output. So if you have a DAC that is capable of generating a [-5V,+5V] output you will be able to generate an analogue signal with the same voltage range, if you need it. Take care that most of the DACs are with current output and the output voltage range is determined by resistors tied to ground at the DAC output so you can choose your output swing with some freedom.

[Altera_Forum]

Hi everybody, 

I just want to inform you that I've finished work on my digital LowPass IIR Filter with success. The suggestions, advices and proposiotions that I received from you helped me a lot. Thank you for your time and effort.  Sincerely yours, Bojan :D

[Altera_Forum]

If you want more accurate filter response then i would suggest you to go for 32-bit representation of coefficients as per IEEE754 -Floating point Standard. You can use Floating point arithmetic unit core that altera provides to handle the Multiplications and additions in pipeline fashion to avoid latencies.

[Altera_Forum]

--- Quote Start ---   b0y(n)=a0x(n)+a1x(n-1)+...+a7x(n-7)+b1y(n-1)+b2y(n-2)+...+b7y(n-7)   I want to know which is the best way to represent coefficients ai, bi, i=0...7? Maybe like a signed number with a fixed point?   --- Quote End ---     Yes. In fact other than fixed point, you don't have any choice while working on FPGA.     --- Quote Start ---   And with how many bits? Is it 16bits enough?  --- Quote End ---     The precision depends on your application. For example, if you want to export the output to a 12-bit port, probably you would like to use 16-bit coefficients while calculating the output (as you would be scaling down your output later on). If you are just making a generic filter for your own testing purposes, you can easily check the performance with a 12-16 bit coeff filter.

[Altera_Forum]

Greetings Koce, I don't know how far you got with this so some of this may be known to you: To implement the filter on a FPGA using DSP builder, you need a series of delay lines which represent the (n-1), (n-2), etc, taps. Signed integer constants, one for every co-efficient (You could also use signed fractional constants to approximate a floating point number). Then using a multiplier block for every coefficient, you then multiply the coefficient with the corresponding delay tap. Then add the result all up using a parallel adder. Of course there are DSP builder blocks that have multiple delay taps and combinations of adders and multipliers. There is also a trick to reducing the amount of resources used if you have a symmetrical filter, and that is to add the outputs of the delay lines that feed the same value coefficient before they are multiplied with it, then you need less multipliers and less inputs on your parallel adder. If you need more clarification please send me an email on kmichaelides@blackrosernd.com