Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

M9K Block RAM calculation

Altera_Forum
Honored Contributor II
‎02-29-2012 12:09 PM
1,412 Views

Hi All advanced: 

i use EP3C16Q240C8 FPGA,and created some Block RAM in my design, 

but Quartus tool report M9K utilization is very strange. 

 

Block RAM describe as below: 

1.Single Port RAM,width = 144 , Depth = 512 , Size = 73728bits , 

73728/(9X1024) = 8 , compilation and report total use eight M9K , it is reasonable 

2.Single Port RAM,width = 144 , Depth = 64 , Size = 9126bits ,  

9216/(9X1024) = 1 , but compilation and report total use four M9K , it is unreasonable 

 

so how to calculate M9K Block RAM ? 

Ex:9216bits = ? M9k
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎02-29-2012 01:23 PM
624 Views

One M9K block data bus maximum width is 36 bits, so You won't be able to use wider than that. Check http://www.altera.com/literature/hb/cyc3/cyc3_ciii51004.pdf

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-01-2012 01:20 AM
624 Views

ok,very gratitude your answer

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.