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hello everyone and happy new year.
http://www.alteraforum.com/forum/attachment.php?attachmentid=11708&stc=1 I'm on a new design with MAX 10 FPGA (16k logic & packaging F256). I'm using the Bank 3 & 4 (They are optimised for LVDS Transition ) . But, a Few pins of them are make as RX ,not TX & RX . Are they only LVDS receiver capable ? :confused: end where do you find the information about it ?:confused: all the best, thank you all for your help. steven le mazouLink Copied
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did find my reply in this PDF 'PCG-01018-1.5 (MAX® 10 FPGA Device Family Pin Connection Guidelines)'
--- Quote Start --- hello everyone and happy new year. http://www.alteraforum.com/forum/attachment.php?attachmentid=11708&stc=1 I'm on a new design with MAX 10 FPGA (16k logic & packaging F256). I'm using the Bank 3 & 4 (They are optimised for LVDS Transition ) . But, a Few pins of them are make as RX ,not TX & RX . Are they only LVDS receiver capable ? :confused: end where do you find the information about it ?:confused: all the best, thank you all for your help. steven le mazou --- Quote End ---- Mark as New
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I did Find my information in this PDF (MAX® 10 FPGA Device Family Pin Connection Guidelines (PCG-01018-1.5))

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