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MAX 10 PLL input and output clocks warnings

Ian_Gibb
Novice
154 Views

Device Max10M40DA256

Nios + SDRAM + application IP on avalon bus

I get warnings on the PLL clocks about the input clock to PLL inclock[0] and an output clock to the SDRAM CK input. Only one PLL is used generating 2 clock outputs. One output for the Nios and one for the SDRAM clk output. Both 100MHz from 25MHz input clk

The PLL input clock is from pin_m3, which is CLK0 input. When built i get warnings for inclock to PLL.

I also get warnings for the SDRAM output clock

How is best to resolve these?

what is the correct way to drive PLL input from external clock input?

what is correct way to generate SDRAM clock from PLL?

Compiler output ..

Warning (15055): PLL "NiosMipr2:u0|NiosMipr2_pll:pll|NiosMipr2_pll_altpll_57g2:sd1|pll7" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
Info (15024): Input port INCLK[0] of node "NiosMipr2:u0|NiosMipr2_pll:pll|NiosMipr2_pll_altpll_57g2:sd1|pll7" is driven by SYS_CLK~inputclkctrl which is OUTCLK output port of Clock control block type node SYS_CLK~inputclkctrl


Warning (15064): PLL "NiosMipr2:u0|NiosMipr2_pll:pll|NiosMipr2_pll_altpll_57g2:sd1|pll7" output port clk[1] feeds output pin "SDRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

 

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1 Solution
Ian_Gibb
Novice
128 Views

Hi Ash,

Thanks for this, thats all good now. I also found i had declared the input clock as a global clock which it did not like ... i assume because it no longer exclusive to the PLL input. With that and your notes above i no longer get these warnings.

Many thanks for your help.

Ian

 

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4 Replies
Ash_R_Intel
Employee
141 Views

Hi Ian,

Though you are using the CLK0 pin, the PLL instance location also matters here. You will not see this warning if CLK0 is driving either PLL1 or PLL3. If PLL2 or PLL4 got instantiated, then you will see this warning. Please confirm which PLL has got instantiated in your design.

You may constraint the SDRAM and NIOS IP placement such that the dedicated PLL gets instantiated.


Regards.


Ian_Gibb
Novice
138 Views

Hi Ash,

Thanks for your comments, which make sense. I was kind of thinking that the compiler would make a logical decision on allocating the PLL from the i/p clock source  ... maybe.

Can you clarify how to define which PLL to use when the instantiation is done, i am struggling to find this setting ?

 

I have fixed the SDRAM clock output by instantiating the PLL outside the NIOS IP and passing through a ALTCLKCNTRL to output the SDRAM from pll_c0 to the dedicated PLLOUT pin, PLL_L_CLKOUTp

So I need to use the associated input clock to that PLL to fix the other warning.. But the PLL_L_CLKOUTp are named B, L, R, T rather than 1,2,3,4 ?! (from the device pinout files)

How do i know which is which?

Regards

Ian

 

 

Ash_R_Intel
Employee
132 Views

Hi Ian,


You can assign location to the PLL instance in the Assignment Editor. 

1) Go to Assignment Editor. 

2) Double click on <<new>> row in To column.

3) Using Node finder, select the PLL instance.

4) In Assignment Name column, choose Location.

5) In Value column, first select the Element as PLL and then the Location as desired.


The PLL_CLKOUT pins are named as B-Bottom, R-Right, L-Left and T-Top based on PLL locations in the package. Please refer Figure 10 of Intel MAX 10 Clocking and PLL User Guide for the PLL locations: https://www.intel.com/content/www/us/en/programmable/documentation/mcn1395213337540.html#mcn13957135...


Regards.


Ian_Gibb
Novice
129 Views

Hi Ash,

Thanks for this, thats all good now. I also found i had declared the input clock as a global clock which it did not like ... i assume because it no longer exclusive to the PLL input. With that and your notes above i no longer get these warnings.

Many thanks for your help.

Ian

 

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