There a few things unclear to me in the External Memory Interface for MAX 10.
I want to interface a MAX10 10M16 in F256 package to a 1Gb DDR2 DRAM (MT47H128M16). According to the UG-MAX10EMI I can use banks 5 and 6 for DDR interface in that package with one 8-bit DQ group each. So far so good. Both banks have a total of 48 pins and the DDR needs 45 or 47 depending whether the DQSs are SE or differential. Still good. Each bank has 9 DQ pins, a DM pin and a DQS/DQSn pair. This leaves 24 pins for the address/command and control signals that are actually 25. This makes me think I can assign any unused DQ or the DQSn pins to address and control but haven't found that explicitly stated. Can anyone shed some light on this? Thanks in advance Additionally, table 9 (ch. 3.3) lists "Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in Certain Device Packages" - not clear if they are not available as Memory interface os as additional I/O after the Mem Interface is assigned.