MAX II Programmable Register

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

MAX II Programmable Register

974 Views

Hi All,

I'm working with a MAX II EPM1270. In the MAX II documentation the register inside each logic element (LE) is referred to as programmable, capable of D, T, JK, or SR operation. What's meant by this? Is the register itself programmable (are there configuration bits associated with it)? Or, is this an LE level definition, meaning that each mode the register is capable of implies a specific allocation of the LE resources, like the Set/Reset signals of an SR are always from the LAB wide inputs.

It would be nice if there were a truth table or tables for the register.

Thanks,

Chris

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.