Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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MAX II vs MAX V??

FCaña
Beginner
1,234 Views

We have an old design using MAX II family, particulary the CPLD EPM2210F256I5N and we want to improve this design usign the MAX V family with the CPLD 5M2210ZF256I5N. I know that it is full compatible pinout but I want to know if there are any other problem or changes includes in this improvement, like software changes or something different.

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5 Replies
HBhat2
New Contributor II
957 Views

Hi,

I found a similar discussion link

https://forums.intel.com/s/question/0D50P00003yyNpBSAU/max-ii-to-max-v-migration

 

Also, you need to use the proper Quartus tool version which supports Max V devices

 

With regards,

HPB

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FCaña
Beginner
957 Views

Hello,

 

Thank you for the information but in that discussion they don´t response the main issue.

Can you give me additional information?

 

Thanks you in advance

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JohnT_Intel
Employee
957 Views

Hi,

 

There will no be any problem as the design will be re-synthesis for Max V design as the architecture for this device is different compare to Max II device. The performance will also be better.

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FCaña
Beginner
957 Views

Hi,

So, if i change the CPLD, the software will automatically re-synthesis or I will do it again for the MAX V?

Thanks in advance

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JohnT_Intel
Employee
957 Views

Hi,

 

You will need to change the device used for your Quartus design before re-compiling the design.

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