MAX V: Using an input clock signal for logic, and sending it back out for clocking

[Altera_Forum]

Hi, 

I'm using a MAX V CPLD (5M240ZM68C5), and sending a clock signal into a special function clock pin (CLK1, Pin E1). This signal is being used to: A) driving internal logic, and B) ideally, routed back out for external circuitry to use. I am, however, unable to have this clock signal appear externally on an output pin. Is there a reason? Is there a flag I can set that makes this possible?  Thanks in advance, Shiva

[Altera_Forum]

--- Quote Start ---   I am, however, unable to have this clock signal appear externally on an output pin.   --- Quote End ---   What have you tried? An input can be routed to an output using a single line of code, eg., VHDL   clkout <= clkin;   So long as you have pin assignments for clkin and clkout, this should work.  However, Quartus will likely warn that clkout is not derived from a dedicated PLL clock output and is likely to have excess jitter (at least it does on the FPGA devices). Depending on your application, you can choose to ignore that.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

Thanks for the feedback. I've tried just what you've suggested, but doesn't work. Using your descriptors, I've created a clkout which is std_logic out, and clkin is a std_logic in. I can push other non-clock signals onto the clkout pin, but not the clock signal coming in on a special function clock pin.  If you can think of other debug ideas I'd be interested in learning about them, Thanks very much, Shiva      --- Quote Start ---  What have you tried? An input can be routed to an output using a single line of code, eg., VHDL   clkout <= clkin;   So long as you have pin assignments for clkin and clkout, this should work.  However, Quartus will likely warn that clkout is not derived from a dedicated PLL clock output and is likely to have excess jitter (at least it does on the FPGA devices). Depending on your application, you can choose to ignore that.  Cheers, Dave  --- Quote End ---