MAX10 10M04 - Not enough logic elements to use the ADC block?

[James44]

Hi - I'm new to FPGA programming. I'm using the MAX10 10M04SAE144I7G on a board I made. I've gotten as far as programming it to blink LEDs and read pushbuttons now I'm trying to read an analog signal through an ADC pin.

From Intel's online tutorials to setup the ADC I used Quartus Platform Designer and created a block symbol file with the following components, modular ADC core Intel FPGA IP, ALTPLL Intel FPGA IP and JTAG to Avalon Master Bridge. When I go back to Quartus, load in the block symbol file and compile it says "Can't fit design in device". The total logic elements used says 7,432 when the 10M04 only has 4,032 logic elements available.

Is there a way to reduce the amount of logic elements that the ADC block uses?

What's the most simple way to read 1 analog input that uses the least amount of logic elements? Any simple vhdl code examples would be very helpful.

Thank you

[FvM]

The basic ADC block needs about 480 LE, less than 1/8 of 10M04 capacity. It's apparently not the ADC IP as such but other stuff that's consuming the logic resources in your design.

[James44]

Thanks for your response @FvM 

I've attached the vhdl code generated by the Platform Designer and all the submodules associated with it.

Is it possible the Platform Designer is incorporating too many submodules? 

Are there sections of it I can delete?

Thanks again

[ShengN_Intel]

Hi,

May I know which design example tutorials file you're following?

Thanks,

Regards,

Sheng

[James44]

Hi @ShengN_Intel

I was following this tutorial
https://youtu.be/0oO1RFa-4Xk?feature=shared

Thanks

[ShengN_Intel]

Hi,

The high LE consumptions is because of enabling the Debug Path in Modular ADC core. May check the tutorial video link provided which had been used about 4640 LEs far exceeded the limit of 4,032 LEs.

If disabling the Debug Path, the LE consumptions will be reduced to about 1k+

Thanks,

Regards,

Sheng

[James44]

Ok thanks. I just regenerated a new .bdf file without the debug path but now I'm having troubles compiling because of these messages:

Error (12181): Top-level entity "adc4" is ambiguous

Error (12180): Instance could be entity "adc4" in file adc4/synthesis/adc4.vhd compiled in library adc4

Error (12180): Instance could be entity "adc4" in file adc4.bdf compiled in library work

Error (12153): Can't elaborate top-level user hierarchy

What file is supposed to be set to the Top- level entity?

Thanks 

[ShengN_Intel · Accepted solution]

Hi,

Try to set the bdf file adc4.bdf to other name.

Thanks,

Regards,

Sheng

[James44]

Thank you so much @ShengN_Intel 

Both of those solutions fixed the problem. The .bdf file looks like it has to be a different name than the .qip file.

Also disabling the debug path and compiling now only uses 1,102 logic elements.

Thank you

[givememessage]

10M04SAE144I7G $18, contact: jack@aceicc.com