Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

MAX10 ADC sample store with threshold violation detection core

Altera_Forum
Honored Contributor II
‎09-06-2016 08:22 PM
1,251 Views

Hi, 

I succesfully followed this example http://www.alterawiki.com/uploads/c/cd/max10_adc_with_threshold_violation_detection_v1.pdf. 

Now trying to do something "usefull": to turn on a LED when out of thesholds. 

I wrote a controller with Avalon ST Sink interface for the threshold related signals and Avalon MM Master interface to write to a PIO Avalon MM Slave. (find attached). 

On my board the controller runs a 25MHz system clock, the ADC gets 2MHz from PLL and peform 25KHz sampling. I monitor 4 channels so it should take about 1000 clocks of the controller to expect the sequencer to finish the cycle and decide about threshold violation. 

Since I want the LED to stay on while thrshold violated I "latch" the valid signal with a 25bit counter that should give more than a second for another valid to come. It doesn't work! 

Can someone take a look at this?
adc_controller.vhd
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.